A bit level systolic array for computing the convolution operation is described. The circuit in question is highly regular and ideally suited to VLSI chip design. It is also optimized in the sense that all the cells contribute to the computation on each clock cycle. This makes the array almost four times more efficient than one which was previously described.
|Number of pages||6|
|Journal||IEE Proceedings, Part F: Communications, Radar and Signal Processing|
|Publication status||Published - 01 Oct 1984|