OPTIMISED BIT LEVEL SYSTOLIC ARRAY FOR CONVOLUTION.

J.V. McCanny, D. Phil, J.G. McWhirter, K. Wood

Research output: Contribution to journalArticle

25 Citations (Scopus)

Abstract

A bit level systolic array for computing the convolution operation is described. The circuit in question is highly regular and ideally suited to VLSI chip design. It is also optimized in the sense that all the cells contribute to the computation on each clock cycle. This makes the array almost four times more efficient than one which was previously described.
Original languageEnglish
Pages (from-to)632-637
Number of pages6
JournalIEE Proceedings, Part F: Communications, Radar and Signal Processing
Volume131
Issue number6
Publication statusPublished - 01 Oct 1984

Bibliographical note

Copyright 2004 Elsevier B.V., All rights reserved.

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