### Abstract

Language | English |
---|---|

Pages | 2794-2806 |

Journal | IEEE Transactions on Computers |

Volume | 65 |

Issue number | 9 |

Early online date | 06 Nov 2015 |

DOIs | |

Publication status | Published - 01 Sep 2016 |

### Fingerprint

### Keywords

- Fully homomorphic encryption
- Large integer multiplication
- low Hamming weight
- FPGA
- cryptography

### Cite this

*IEEE Transactions on Computers*,

*65*(9), 2794-2806. https://doi.org/10.1109/TC.2015.2498606

}

*IEEE Transactions on Computers*, vol. 65, no. 9, pp. 2794-2806. https://doi.org/10.1109/TC.2015.2498606

**Optimised Multiplication Architectures for Accelerating Fully Homomorphic Encryption.** / Cao, Xiaolin; Moore, Ciara; O'Neill, Maire; O'Sullivan, Elizabeth; Hanley, Neil.

Research output: Contribution to journal › Article

TY - JOUR

T1 - Optimised Multiplication Architectures for Accelerating Fully Homomorphic Encryption

AU - Cao, Xiaolin

AU - Moore, Ciara

AU - O'Neill, Maire

AU - O'Sullivan, Elizabeth

AU - Hanley, Neil

PY - 2016/9/1

Y1 - 2016/9/1

N2 - Large integer multiplication is a major performance bottleneck in fully homomorphic encryption (FHE) schemes over the integers. In this paper two optimised multiplier architectures for large integer multiplication are proposed. The first of these is a low-latency hardware architecture of an integer-FFT multiplier. Secondly, the use of low Hamming weight (LHW) parameters is applied to create a novel hardware architecture for large integer multiplication in integer-based FHE schemes. The proposed architectures are implemented, verified and compared on the Xilinx Virtex-7 FPGA platform. Finally, the proposed implementations are employed to evaluate the large multiplication in the encryption step of FHE over the integers. The analysis shows a speed improvement factor of up to 26.2 for the low-latency design compared to the corresponding original integer-based FHE software implementation. When the proposed LHW architecture is combined with the low-latency integer-FFT accelerator to evaluate a single FHE encryption operation, the performance results show that a speed improvement by a factor of approximately 130 is possible.

AB - Large integer multiplication is a major performance bottleneck in fully homomorphic encryption (FHE) schemes over the integers. In this paper two optimised multiplier architectures for large integer multiplication are proposed. The first of these is a low-latency hardware architecture of an integer-FFT multiplier. Secondly, the use of low Hamming weight (LHW) parameters is applied to create a novel hardware architecture for large integer multiplication in integer-based FHE schemes. The proposed architectures are implemented, verified and compared on the Xilinx Virtex-7 FPGA platform. Finally, the proposed implementations are employed to evaluate the large multiplication in the encryption step of FHE over the integers. The analysis shows a speed improvement factor of up to 26.2 for the low-latency design compared to the corresponding original integer-based FHE software implementation. When the proposed LHW architecture is combined with the low-latency integer-FFT accelerator to evaluate a single FHE encryption operation, the performance results show that a speed improvement by a factor of approximately 130 is possible.

KW - Fully homomorphic encryption

KW - Large integer multiplication

KW - low Hamming weight

KW - FPGA

KW - cryptography

U2 - 10.1109/TC.2015.2498606

DO - 10.1109/TC.2015.2498606

M3 - Article

VL - 65

SP - 2794

EP - 2806

JO - IEEE Transactions on Computers

T2 - IEEE Transactions on Computers

JF - IEEE Transactions on Computers

SN - 0018-9340

IS - 9

ER -