Optimised Multiplication Architectures for Accelerating Fully Homomorphic Encryption

Xiaolin Cao, Ciara Moore, Maire O'Neill, Elizabeth O'Sullivan, Neil Hanley

Research output: Contribution to journalArticle

11 Citations (Scopus)

Abstract

Large integer multiplication is a major performance bottleneck in fully homomorphic encryption (FHE) schemes over the integers. In this paper two optimised multiplier architectures for large integer multiplication are proposed. The first of these is a low-latency hardware architecture of an integer-FFT multiplier. Secondly, the use of low Hamming weight (LHW) parameters is applied to create a novel hardware architecture for large integer multiplication in integer-based FHE schemes. The proposed architectures are implemented, verified and compared on the Xilinx Virtex-7 FPGA platform. Finally, the proposed implementations are employed to evaluate the large multiplication in the encryption step of FHE over the integers. The analysis shows a speed improvement factor of up to 26.2 for the low-latency design compared to the corresponding original integer-based FHE software implementation. When the proposed LHW architecture is combined with the low-latency integer-FFT accelerator to evaluate a single FHE encryption operation, the performance results show that a speed improvement by a factor of approximately 130 is possible.
LanguageEnglish
Pages2794-2806
JournalIEEE Transactions on Computers
Volume65
Issue number9
Early online date06 Nov 2015
DOIs
Publication statusPublished - 01 Sep 2016

Fingerprint

Homomorphic Encryption
Cryptography
Multiplication
Integer
Latency
Hamming Weight
Fast Fourier transforms
Hardware Architecture
Encryption
Multiplier
Hardware
Architecture
Particle accelerators
Evaluate
Field programmable gate arrays (FPGA)
Accelerator
Field Programmable Gate Array
Software

Keywords

  • Fully homomorphic encryption
  • Large integer multiplication
  • low Hamming weight
  • FPGA
  • cryptography

Cite this

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title = "Optimised Multiplication Architectures for Accelerating Fully Homomorphic Encryption",
abstract = "Large integer multiplication is a major performance bottleneck in fully homomorphic encryption (FHE) schemes over the integers. In this paper two optimised multiplier architectures for large integer multiplication are proposed. The first of these is a low-latency hardware architecture of an integer-FFT multiplier. Secondly, the use of low Hamming weight (LHW) parameters is applied to create a novel hardware architecture for large integer multiplication in integer-based FHE schemes. The proposed architectures are implemented, verified and compared on the Xilinx Virtex-7 FPGA platform. Finally, the proposed implementations are employed to evaluate the large multiplication in the encryption step of FHE over the integers. The analysis shows a speed improvement factor of up to 26.2 for the low-latency design compared to the corresponding original integer-based FHE software implementation. When the proposed LHW architecture is combined with the low-latency integer-FFT accelerator to evaluate a single FHE encryption operation, the performance results show that a speed improvement by a factor of approximately 130 is possible.",
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Optimised Multiplication Architectures for Accelerating Fully Homomorphic Encryption. / Cao, Xiaolin; Moore, Ciara; O'Neill, Maire; O'Sullivan, Elizabeth; Hanley, Neil.

In: IEEE Transactions on Computers, Vol. 65, No. 9, 01.09.2016, p. 2794-2806.

Research output: Contribution to journalArticle

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