Optimised multiply/accumulate architecture for very high throughput rate digital filters

B. P. McGovern, R. F. Woods, C. McAllister

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

A new modified circuit for implementing high performance IIR filters based on a pipelined multiply-accumulate (MAC) processor is proposed. Clever deployment of latches in the circuit allows the results to be generated once every cycle thereby providing increased performance with reduced size and power consumption over previously designed circuits.

Original languageEnglish
Pages (from-to)1135-1136
Number of pages2
JournalElectronics Letters
Volume31
Issue number14
DOIs
Publication statusPublished - 06 Jul 1995

Keywords

  • Digital filters
  • Pipeline processing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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