Abstract
Lattice-based cryptography (LBC) is one of the most promising classes of post-quantum cryptography (PQC) that is being considered for standardisation. This paper proposes an optimised schoolbook polynomial multiplication for compact
LBC. We exploit the symmetric nature of Gaussian noise for bit reduction. Additionally, a single FPGA DSP block is used for two parallel multiplication operations per clock cycle. These optimisations enable a significant 2.2 speedup along with reduced resources for dimension n = 256. The overall fficiency (throughput per slice) is 1.28 higher than the conventional schoolbook polynomial multiplication, as well as contributing to a more compact LBC system as compared to previously reported designs. The results targeting the FPGA platform show that the proposed design can achieve both high hardware efficiency with reduced hardware area costs.
LBC. We exploit the symmetric nature of Gaussian noise for bit reduction. Additionally, a single FPGA DSP block is used for two parallel multiplication operations per clock cycle. These optimisations enable a significant 2.2 speedup along with reduced resources for dimension n = 256. The overall fficiency (throughput per slice) is 1.28 higher than the conventional schoolbook polynomial multiplication, as well as contributing to a more compact LBC system as compared to previously reported designs. The results targeting the FPGA platform show that the proposed design can achieve both high hardware efficiency with reduced hardware area costs.
Original language | English |
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Pages (from-to) | 1-5 |
Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Early online date | 28 Jun 2019 |
DOIs | |
Publication status | Early online date - 28 Jun 2019 |