Optimized circuits for implementing high-performance bit-parallel IIR filters are presented. Circuits constructed mainly from simple carry save adders and based on most-significant-bit (MSB) first arithmetic are described. Two methods resulting in systems which are 100% efficient in that they are capable of sampling data every cycle are presented. In the first approach the basic circuit is modified so that the level of pipelining used is compatible with the small, but fixed, latency associated with the computation in question. This is achieved through insertion of pipeline delays (half latches) on every second row of cells. This produces an area-efficient solution in which the throughput rate is determined by a critical path of 76 gate delays. A second approach combines the MSB first arithmetic methods with the scattered look-ahead methods. Important design issues are addressed, including wordlength truncation, overflow detection, and saturation.
|Title of host publication||Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors|
|Place of Publication||LOS ALAMITOS|
|Publisher||IEEE Computer Society|
|Number of pages||5|
|Publication status||Published - 01 Sep 1990|
|Event||1990 INTERNATIONAL CONF ON COMPUTER DESIGN : VLSI IN COMPUTERS AND PROCESSORS ( ICCD 90 ) - CAMBRIDGE, United States|
Duration: 17 Sep 1990 → 19 Sep 1990
|Conference||1990 INTERNATIONAL CONF ON COMPUTER DESIGN : VLSI IN COMPUTERS AND PROCESSORS ( ICCD 90 )|
|Period||17/09/1990 → 19/09/1990|
McNally, O. C., McCanny, J. V., & Woods, R. F. (1990). Optimized bit level architectures for IIR filtering. In Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors (pp. 302-306). IEEE Computer Society.