Parallel implementation of finite difference schemes for the plate equation on a FPGA-based multi-processor array

E. Motuk*, R. Woods, S. Bilbao

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The computational complexity of the finite difference (FD) schemes for the solution of the plate equation prevents them from being used in musical applications. The explicit FD schemes can be parallelized to run on multi-processor arrays for achieving real-time performance. Field Programmable Gate Arrays (FPGAs) provide an ideal platform for implementing these architectures with the advantages of low-power and small form factor. The paper presents a design for implementing FD schemes for the plate equation on a multi-processor architecture on a FPGA device. The results show that 64 processing elements can be accommodated on a Xilinx X2VP50 device, achieving 487 kHz throughput for a square FD grid of 50×50 points.

Original languageEnglish
Title of host publication13th European Signal Processing Conference, EUSIPCO 2005
Pages1846-1849
Number of pages4
Publication statusPublished - 01 Dec 2005
Event13th European Signal Processing Conference, EUSIPCO 2005 - Antalya, Turkey
Duration: 04 Sep 200508 Sep 2005

Conference

Conference13th European Signal Processing Conference, EUSIPCO 2005
CountryTurkey
CityAntalya
Period04/09/200508/09/2005

ASJC Scopus subject areas

  • Signal Processing

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  • Cite this

    Motuk, E., Woods, R., & Bilbao, S. (2005). Parallel implementation of finite difference schemes for the plate equation on a FPGA-based multi-processor array. In 13th European Signal Processing Conference, EUSIPCO 2005 (pp. 1846-1849)