Very high-speed and low-area hardware architectures of the SHACAL-1 encryption algorithm are presented in this paper. The SHACAL algorithm was a submission to the New European Schemes for Signatures, Integrity and Encryption (NESSIE) project and it is based on the SHA-1 hash algorithm. Sub-pipelined SHACAL-1 encryption and decryption architectures are described and when implemented on Virtex-II XC2V4000FPGA devices, run at a throughput of 23 Gbps. In addition, fully pipelined and iterative architectures of the algorithm are presented. The SHACAL-1 decryption algorithm is derived and also presented in the paper, since it was not provided in the submission to NESSIE.
|Title of host publication||New Algorithms, Architectures and Applications for Reconfigurable Computing|
|Editors||W. Rosenstiel, P. Lysaght|
|Number of pages||14|
|ISBN (Print)||1402031270, 9781402031274|
|Publication status||Published - 01 Dec 2005|
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