Performance and Fault Tolerance of Preconditioned Iterative Solvers on Low-Power ARM Architectures

Jose I. Aliaga; Sandra Catalan; Charalampos Chalios; Dimitrios S. Nikolopoulos; Enrique S. Quintana-Orti

Performance and Fault Tolerance of Preconditioned Iterative Solvers on Low-Power ARM Architectures

Jose I. Aliaga, Sandra Catalan, Charalampos Chalios, Dimitrios S. Nikolopoulos, Enrique S. Quintana-Orti

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Abstract

As the complexity of computing systems grows, reliability and energy are two crucial challenges asking for holistic solutions. In this paper, we investigate the interplay among concurrency, power dissipation, energy consumption and voltage-frequency scaling for a key numerical kernel for the solution of sparse linear systems. Concretely, we leverage a task-parallel implementation of the Conjugate Gradient method, equipped with an state-of-the-art pre-conditioner embedded in the ILUPACK software, and target a low-power multi core processor from ARM.In addition, we perform a theoretical analysis on the impact of a technique like Near Threshold Voltage Computing (NTVC) from the points of view of increased hardware concurrency and error rate.

Original language	English
Title of host publication	Workshop on Energy and Resilience in Parallel Programming (ERPP): In conjunction with the ParCo'15 Conference
Number of pages	9
Publication status	Published - Sept 2015
Event	ParCo'15 Conference - Edinburgh, United Kingdom Duration: 01 Sept 2015 → 04 Sept 2015

Conference

Conference	ParCo'15 Conference
Country/Territory	United Kingdom
City	Edinburgh
Period	01/09/2015 → 04/09/2015

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Performance and Fault Tolerance of Preconditioned Iterative Solvers on Low-Power ARM Architectures
Copyright the authors 2015.
Accepted author manuscript, 179 KBLicence: Unspecified

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@inproceedings{9a4cfb75898946838ecc46357f9753a3,

title = "Performance and Fault Tolerance of Preconditioned Iterative Solvers on Low-Power ARM Architectures",

abstract = "As the complexity of computing systems grows, reliability and energy are two crucial challenges asking for holistic solutions. In this paper, we investigate the interplay among concurrency, power dissipation, energy consumption and voltage-frequency scaling for a key numerical kernel for the solution of sparse linear systems. Concretely, we leverage a task-parallel implementation of the Conjugate Gradient method, equipped with an state-of-the-art pre-conditioner embedded in the ILUPACK software, and target a low-power multi core processor from ARM.In addition, we perform a theoretical analysis on the impact of a technique like Near Threshold Voltage Computing (NTVC) from the points of view of increased hardware concurrency and error rate.",

author = "Aliaga, {Jose I.} and Sandra Catalan and Charalampos Chalios and Nikolopoulos, {Dimitrios S.} and Quintana-Orti, {Enrique S.}",

year = "2015",

month = sep,

language = "English",

booktitle = "Workshop on Energy and Resilience in Parallel Programming (ERPP): In conjunction with the ParCo'15 Conference",

note = "ParCo'15 Conference ; Conference date: 01-09-2015 Through 04-09-2015",

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TY - GEN

T1 - Performance and Fault Tolerance of Preconditioned Iterative Solvers on Low-Power ARM Architectures

AU - Aliaga, Jose I.

AU - Catalan, Sandra

AU - Chalios, Charalampos

AU - Nikolopoulos, Dimitrios S.

AU - Quintana-Orti, Enrique S.

PY - 2015/9

Y1 - 2015/9

N2 - As the complexity of computing systems grows, reliability and energy are two crucial challenges asking for holistic solutions. In this paper, we investigate the interplay among concurrency, power dissipation, energy consumption and voltage-frequency scaling for a key numerical kernel for the solution of sparse linear systems. Concretely, we leverage a task-parallel implementation of the Conjugate Gradient method, equipped with an state-of-the-art pre-conditioner embedded in the ILUPACK software, and target a low-power multi core processor from ARM.In addition, we perform a theoretical analysis on the impact of a technique like Near Threshold Voltage Computing (NTVC) from the points of view of increased hardware concurrency and error rate.

AB - As the complexity of computing systems grows, reliability and energy are two crucial challenges asking for holistic solutions. In this paper, we investigate the interplay among concurrency, power dissipation, energy consumption and voltage-frequency scaling for a key numerical kernel for the solution of sparse linear systems. Concretely, we leverage a task-parallel implementation of the Conjugate Gradient method, equipped with an state-of-the-art pre-conditioner embedded in the ILUPACK software, and target a low-power multi core processor from ARM.In addition, we perform a theoretical analysis on the impact of a technique like Near Threshold Voltage Computing (NTVC) from the points of view of increased hardware concurrency and error rate.

M3 - Conference contribution

BT - Workshop on Energy and Resilience in Parallel Programming (ERPP): In conjunction with the ParCo'15 Conference

T2 - ParCo'15 Conference

Y2 - 1 September 2015 through 4 September 2015

ER -

Performance and Fault Tolerance of Preconditioned Iterative Solvers on Low-Power ARM Architectures

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