As the complexity of computing systems grows, reliability and energy are two crucial challenges asking for holistic solutions. In this paper, we investigate the interplay among concurrency, power dissipation, energy consumption and voltage-frequency scaling for a key numerical kernel for the solution of sparse linear systems. Concretely, we leverage a task-parallel implementation of the Conjugate Gradient method, equipped with an state-of-the-art pre-conditioner embedded in the ILUPACK software, and target a low-power multi core processor from ARM.In addition, we perform a theoretical analysis on the impact of a technique like Near Threshold Voltage Computing (NTVC) from the points of view of increased hardware concurrency and error rate.
|Title of host publication||Workshop on Energy and Resilience in Parallel Programming (ERPP): In conjunction with the ParCo'15 Conference|
|Number of pages||9|
|Publication status||Published - Sep 2015|
|Event||ParCo'15 Conference - Edinburgh, United Kingdom|
Duration: 01 Sep 2015 → 04 Sep 2015
|Period||01/09/2015 → 04/09/2015|
Aliaga, J. I., Catalan, S., Chalios, C., Nikolopoulos, D. S., & Quintana-Orti, E. S. (2015). Performance and Fault Tolerance of Preconditioned Iterative Solvers on Low-Power ARM Architectures. In Workshop on Energy and Resilience in Parallel Programming (ERPP): In conjunction with the ParCo'15 Conference