Performance and Fault Tolerance of Preconditioned Iterative Solvers on Low-Power ARM Architectures

Jose I. Aliaga, Sandra Catalan, Charalampos Chalios, Dimitrios S. Nikolopoulos, Enrique S. Quintana-Orti

Research output: Chapter in Book/Report/Conference proceedingConference contribution

99 Downloads (Pure)


As the complexity of computing systems grows, reliability and energy are two crucial challenges asking for holistic solutions. In this paper, we investigate the interplay among concurrency, power dissipation, energy consumption and voltage-frequency scaling for a key numerical kernel for the solution of sparse linear systems. Concretely, we leverage a task-parallel implementation of the Conjugate Gradient method, equipped with an state-of-the-art pre-conditioner embedded in the ILUPACK software, and target a low-power multi core processor from ARM.In addition, we perform a theoretical analysis on the impact of a technique like Near Threshold Voltage Computing (NTVC) from the points of view of increased hardware concurrency and error rate.
Original languageEnglish
Title of host publicationWorkshop on Energy and Resilience in Parallel Programming (ERPP): In conjunction with the ParCo'15 Conference
Number of pages9
Publication statusPublished - Sep 2015
EventParCo'15 Conference - Edinburgh, United Kingdom
Duration: 01 Sep 201504 Sep 2015


ConferenceParCo'15 Conference
Country/TerritoryUnited Kingdom


Dive into the research topics of 'Performance and Fault Tolerance of Preconditioned Iterative Solvers on Low-Power ARM Architectures'. Together they form a unique fingerprint.

Cite this