Performance assessment of nanoscale double- and triple- gate FinFETs

Abhinav Kranti, Alastair Armstrong

Research output: Contribution to journalArticle

73 Citations (Scopus)

Abstract

This is the first paper to describe performance assessment of triple and double gate FinFETs for High Performance (HP), Low Operating Power (LOP) and Low Standby Power (LSTP) logic technologies is investigated. The impact of gate work-function, spacer width, lateral source/drain doping gradient, fin aspect ratio, fin thickness on device performance, has been analysed in detail and guidelines are presented to meet ITRS specification at 65 and 45 nm nodes. Optimal design of lateral source/drain doping profile can not only effectively control short channel effects, yielding low off-current, but also achieve low values of intrinsic gate delay.
Original languageEnglish
Pages (from-to)409-421
Number of pages13
JournalSemiconductor Science and Technology
Volume21(4)
Issue number4
DOIs
Publication statusPublished - 01 Feb 2006

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Materials Science(all)
  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics

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