Poster: Reducing the Burden of Parallel Loop Schedulers for Many-core Processors

Mahwish Arif; Hans Vandierendonck

doi:10.1145/3178487.3178517

Poster: Reducing the Burden of Parallel Loop Schedulers for Many-core Processors

Mahwish Arif, Hans Vandierendonck

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

This work proposes a low-overhead half-barrier pattern to schedule fine-grain parallel loops and considers its integration in the Intel OpenMP and Cilkplus schedulers. Experimental evaluation demonstrates that the scheduling overhead of our techniques is 43% lower than Intel OpenMP and 12.1x lower than Cilk. We observe 22% speedup on 48 threads, with a peak of 2.8x speedup.

Original language	English
Title of host publication	Proceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
Publisher	Association for Computing Machinery
Pages	383-384
Number of pages	2
ISBN (Print)	978-1-4503-4982-6
DOIs	https://doi.org/10.1145/3178487.3178517
Publication status	Published - 10 Feb 2018
Event	23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming - Vienna, Austria Duration: 24 Feb 2018 → 28 Feb 2018

Conference

Conference	23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
Abbreviated title	PPoPP'18
Country/Territory	Austria
City	Vienna
Period	24/02/2018 → 28/02/2018

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10.1145/3178487.3178517Licence: Unspecified

Cite this

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title = "Poster: Reducing the Burden of Parallel Loop Schedulers for Many-core Processors",

abstract = "This work proposes a low-overhead half-barrier pattern to schedule fine-grain parallel loops and considers its integration in the Intel OpenMP and Cilkplus schedulers. Experimental evaluation demonstrates that the scheduling overhead of our techniques is 43% lower than Intel OpenMP and 12.1x lower than Cilk. We observe 22% speedup on 48 threads, with a peak of 2.8x speedup.",

author = "Mahwish Arif and Hans Vandierendonck",

year = "2018",

month = feb,

day = "10",

doi = "10.1145/3178487.3178517",

language = "English",

isbn = "978-1-4503-4982-6",

pages = "383--384",

booktitle = "Proceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming",

publisher = "Association for Computing Machinery",

address = "United States",

note = "23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP'18 ; Conference date: 24-02-2018 Through 28-02-2018",

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Arif, M & Vandierendonck, H 2018, Poster: Reducing the Burden of Parallel Loop Schedulers for Many-core Processors. in Proceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming. Association for Computing Machinery, pp. 383-384, 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, Vienna, Austria, 24/02/2018. https://doi.org/10.1145/3178487.3178517

TY - GEN

T1 - Poster: Reducing the Burden of Parallel Loop Schedulers for Many-core Processors

AU - Arif, Mahwish

AU - Vandierendonck, Hans

PY - 2018/2/10

Y1 - 2018/2/10

N2 - This work proposes a low-overhead half-barrier pattern to schedule fine-grain parallel loops and considers its integration in the Intel OpenMP and Cilkplus schedulers. Experimental evaluation demonstrates that the scheduling overhead of our techniques is 43% lower than Intel OpenMP and 12.1x lower than Cilk. We observe 22% speedup on 48 threads, with a peak of 2.8x speedup.

AB - This work proposes a low-overhead half-barrier pattern to schedule fine-grain parallel loops and considers its integration in the Intel OpenMP and Cilkplus schedulers. Experimental evaluation demonstrates that the scheduling overhead of our techniques is 43% lower than Intel OpenMP and 12.1x lower than Cilk. We observe 22% speedup on 48 threads, with a peak of 2.8x speedup.

U2 - 10.1145/3178487.3178517

DO - 10.1145/3178487.3178517

M3 - Conference contribution

SN - 978-1-4503-4982-6

SP - 383

EP - 384

BT - Proceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming

PB - Association for Computing Machinery

T2 - 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming

Y2 - 24 February 2018 through 28 February 2018

ER -

Poster: Reducing the Burden of Parallel Loop Schedulers for Many-core Processors

Abstract

Conference

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