Poster: Reducing the Burden of Parallel Loop Schedulers for Many-core Processors

Mahwish Arif, Hans Vandierendonck

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This work proposes a low-overhead half-barrier pattern to schedule fine-grain parallel loops and considers its integration in the Intel OpenMP and Cilkplus schedulers. Experimental evaluation demonstrates that the scheduling overhead of our techniques is 43% lower than Intel OpenMP and 12.1x lower than Cilk. We observe 22% speedup on 48 threads, with a peak of 2.8x speedup.
Original languageEnglish
Title of host publicationProceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
PublisherAssociation for Computing Machinery (ACM)
Pages383-384
Number of pages2
ISBN (Print)978-1-4503-4982-6
DOIs
Publication statusPublished - 10 Feb 2018
Event23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming - Vienna, Austria
Duration: 24 Feb 201828 Feb 2018

Conference

Conference23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
Abbreviated titlePPoPP'18
CountryAustria
CityVienna
Period24/02/201828/02/2018

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  • Cite this

    Arif, M., & Vandierendonck, H. (2018). Poster: Reducing the Burden of Parallel Loop Schedulers for Many-core Processors. In Proceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (pp. 383-384). Association for Computing Machinery (ACM). https://doi.org/10.1145/3178487.3178517