Power-Capped DVFS and Thread Allocation with ANN Models on Modern NUMA Systems

Satoshi Imamura; Hiroshi Sasaki; Koji Inoue; Dimitrios Nikolopoulos

doi:10.1109/ICCD.2014.6974701

Power-Capped DVFS and Thread Allocation with ANN Models on Modern NUMA Systems

Satoshi Imamura, Hiroshi Sasaki, Koji Inoue, Dimitrios Nikolopoulos

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

541 Downloads (Pure)

Abstract

Abstract—Power capping is an essential function for efficient power budgeting and cost management on modern server systems. Contemporary server processors operate under power caps by using dynamic voltage and frequency scaling (DVFS). However, these processors are often deployed in non-uniform memory
access (NUMA) architectures, where thread allocation between cores may significantly affect performance and power consumption. This paper proposes a method which maximizes performance under power caps on NUMA systems by dynamically optimizing two knobs: DVFS and thread allocation. The method selects the optimal combination of the two knobs with models based on artificial neural network (ANN) that captures the nonlinear effect of thread allocation on performance. We implement
the proposed method as a runtime system and evaluate it with twelve multithreaded benchmarks on a real AMD Opteron based NUMA system. The evaluation results show that our method outperforms a naive technique optimizing only DVFS by up to
67.1%, under a power cap.

Original language	English
Title of host publication	Proceedings of the 32nd IEEE International Conference on Computer Design (ICCD).
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	324-331
ISBN (Electronic)	978-1-4799-6492-5
DOIs	https://doi.org/10.1109/ICCD.2014.6974701
Publication status	Published - 21 Oct 2014
Event	The 32nd IEEE International Conference on Computer Design - Novotel Ambassador Gangnam Hotel, Seoul, Korea, Republic of Duration: 19 Oct 2014 → 22 Oct 2014

Conference

Conference	The 32nd IEEE International Conference on Computer Design
Country/Territory	Korea, Republic of
City	Seoul
Period	19/10/2014 → 22/10/2014

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10.1109/ICCD.2014.6974701

Power-capped DVFS and thread allocation with ANN models on modern NUMA systems
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Accepted author manuscript, 585 KB

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R6410CSC: NanoStreams: A Hardware and Software Stack for Real-Time Analytics on Fast Data Streams
Nikolopoulos, D. (PI), Spence, I. (CoI) & Woods, R. (CoI)
01/08/2013 → 28/02/2017
Project: Research
R1337CSC: ENPOWER
Nikolopoulos, D. (PI) & Woods, R. (CoI)
01/08/2013 → 05/02/2018
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Cite this

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title = "Power-Capped DVFS and Thread Allocation with ANN Models on Modern NUMA Systems",

abstract = "Abstract—Power capping is an essential function for efficient power budgeting and cost management on modern server systems. Contemporary server processors operate under power caps by using dynamic voltage and frequency scaling (DVFS). However, these processors are often deployed in non-uniform memoryaccess (NUMA) architectures, where thread allocation between cores may significantly affect performance and power consumption. This paper proposes a method which maximizes performance under power caps on NUMA systems by dynamically optimizing two knobs: DVFS and thread allocation. The method selects the optimal combination of the two knobs with models based on artificial neural network (ANN) that captures the nonlinear effect of thread allocation on performance. We implementthe proposed method as a runtime system and evaluate it with twelve multithreaded benchmarks on a real AMD Opteron based NUMA system. The evaluation results show that our method outperforms a naive technique optimizing only DVFS by up to67.1%, under a power cap.",

author = "Satoshi Imamura and Hiroshi Sasaki and Koji Inoue and Dimitrios Nikolopoulos",

year = "2014",

month = oct,

day = "21",

doi = "10.1109/ICCD.2014.6974701",

language = "English",

pages = "324--331",

booktitle = "Proceedings of the 32nd IEEE International Conference on Computer Design (ICCD).",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "The 32nd IEEE International Conference on Computer Design ; Conference date: 19-10-2014 Through 22-10-2014",

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Imamura, S, Sasaki, H, Inoue, K & Nikolopoulos, D 2014, Power-Capped DVFS and Thread Allocation with ANN Models on Modern NUMA Systems. in Proceedings of the 32nd IEEE International Conference on Computer Design (ICCD).. Institute of Electrical and Electronics Engineers Inc., pp. 324-331, The 32nd IEEE International Conference on Computer Design, Seoul, Korea, Republic of, 19/10/2014. https://doi.org/10.1109/ICCD.2014.6974701

Power-Capped DVFS and Thread Allocation with ANN Models on Modern NUMA Systems. / Imamura, Satoshi; Sasaki, Hiroshi; Inoue, Koji et al.
Proceedings of the 32nd IEEE International Conference on Computer Design (ICCD).. Institute of Electrical and Electronics Engineers Inc., 2014. p. 324-331.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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T1 - Power-Capped DVFS and Thread Allocation with ANN Models on Modern NUMA Systems

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AU - Inoue, Koji

AU - Nikolopoulos, Dimitrios

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N2 - Abstract—Power capping is an essential function for efficient power budgeting and cost management on modern server systems. Contemporary server processors operate under power caps by using dynamic voltage and frequency scaling (DVFS). However, these processors are often deployed in non-uniform memoryaccess (NUMA) architectures, where thread allocation between cores may significantly affect performance and power consumption. This paper proposes a method which maximizes performance under power caps on NUMA systems by dynamically optimizing two knobs: DVFS and thread allocation. The method selects the optimal combination of the two knobs with models based on artificial neural network (ANN) that captures the nonlinear effect of thread allocation on performance. We implementthe proposed method as a runtime system and evaluate it with twelve multithreaded benchmarks on a real AMD Opteron based NUMA system. The evaluation results show that our method outperforms a naive technique optimizing only DVFS by up to67.1%, under a power cap.

AB - Abstract—Power capping is an essential function for efficient power budgeting and cost management on modern server systems. Contemporary server processors operate under power caps by using dynamic voltage and frequency scaling (DVFS). However, these processors are often deployed in non-uniform memoryaccess (NUMA) architectures, where thread allocation between cores may significantly affect performance and power consumption. This paper proposes a method which maximizes performance under power caps on NUMA systems by dynamically optimizing two knobs: DVFS and thread allocation. The method selects the optimal combination of the two knobs with models based on artificial neural network (ANN) that captures the nonlinear effect of thread allocation on performance. We implementthe proposed method as a runtime system and evaluate it with twelve multithreaded benchmarks on a real AMD Opteron based NUMA system. The evaluation results show that our method outperforms a naive technique optimizing only DVFS by up to67.1%, under a power cap.

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T2 - The 32nd IEEE International Conference on Computer Design

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Power-Capped DVFS and Thread Allocation with ANN Models on Modern NUMA Systems

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Projects

R6410CSC: NanoStreams: A Hardware and Software Stack for Real-Time Analytics on Fast Data Streams

R1337CSC: ENPOWER

R1131CSC: ERA-Net CHIST-ERA

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