Power Efficient DSP Datapath Configuration Methodology for FPGA

Michael McKeown, Roger Woods, John McAllister

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Exploiting the underutilisation of variable-length DSP algorithms during normal operation is vital, when seeking to maximise the achievable functionality of an application within peak power budget. A system level, low power design methodology for FPGA-based, variable length DSP IP cores is presented. Algorithmic commonality is identified and resources mapped with a configurable datapath, to increase achievable functionality. It is applied to a digital receiver application where a 100% increase in operational capacity is achieved in certain modes without significant power or area budget increases. Measured results show resulting architectures requires 19% less peak power, 33% fewer multipliers and 12% fewer slices than existing architectures.
Original languageEnglish
Title of host publication2008 International Conference on Field Programmable Logic and Applications. Proceedings
Pages515-518
Number of pages4
DOIs
Publication statusPublished - Sep 2008
Event2008 IEEE International Conference on Field Programmable Logic and Applications (FPL'08) - Heidelberg, Germany
Duration: 08 Sep 200810 Sep 2008

Publication series

Name
ISSN (Print)1946-147X

Conference

Conference2008 IEEE International Conference on Field Programmable Logic and Applications (FPL'08)
CountryGermany
CityHeidelberg
Period08/09/200810/09/2008

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  • Cite this

    McKeown, M., Woods, R., & McAllister, J. (2008). Power Efficient DSP Datapath Configuration Methodology for FPGA. In 2008 International Conference on Field Programmable Logic and Applications. Proceedings (pp. 515-518) https://doi.org/10.1109/FPL.2008.4629997