Power Efficient DSP Datapath Configuration Methodology for FPGA

Michael McKeown; Roger Woods; John McAllister

doi:10.1109/FPL.2008.4629997

Power Efficient DSP Datapath Configuration Methodology for FPGA

Michael McKeown, Roger Woods, John McAllister

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

Exploiting the underutilisation of variable-length DSP algorithms during normal operation is vital, when seeking to maximise the achievable functionality of an application within peak power budget. A system level, low power design methodology for FPGA-based, variable length DSP IP cores is presented. Algorithmic commonality is identified and resources mapped with a configurable datapath, to increase achievable functionality. It is applied to a digital receiver application where a 100% increase in operational capacity is achieved in certain modes without significant power or area budget increases. Measured results show resulting architectures requires 19% less peak power, 33% fewer multipliers and 12% fewer slices than existing architectures.

Original language	English
Title of host publication	2008 International Conference on Field Programmable Logic and Applications. Proceedings
Pages	515-518
Number of pages	4
DOIs	https://doi.org/10.1109/FPL.2008.4629997
Publication status	Published - Sept 2008
Event	2008 IEEE International Conference on Field Programmable Logic and Applications (FPL'08) - Heidelberg, Germany Duration: 08 Sept 2008 → 10 Sept 2008

Publication series

Name
ISSN (Print)	1946-147X

Conference

Conference	2008 IEEE International Conference on Field Programmable Logic and Applications (FPL'08)
Country/Territory	Germany
City	Heidelberg
Period	08/09/2008 → 10/09/2008

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10.1109/FPL.2008.4629997

Cite this

@inproceedings{42ca48f4043b4381a4a84498813376ce,

title = "Power Efficient DSP Datapath Configuration Methodology for FPGA",

abstract = "Exploiting the underutilisation of variable-length DSP algorithms during normal operation is vital, when seeking to maximise the achievable functionality of an application within peak power budget. A system level, low power design methodology for FPGA-based, variable length DSP IP cores is presented. Algorithmic commonality is identified and resources mapped with a configurable datapath, to increase achievable functionality. It is applied to a digital receiver application where a 100\% increase in operational capacity is achieved in certain modes without significant power or area budget increases. Measured results show resulting architectures requires 19\% less peak power, 33\% fewer multipliers and 12\% fewer slices than existing architectures.",

author = "Michael McKeown and Roger Woods and John McAllister",

year = "2008",

month = sep,

doi = "10.1109/FPL.2008.4629997",

language = "English",

isbn = "978-1-4244-1960-9",

pages = "515--518",

booktitle = "2008 International Conference on Field Programmable Logic and Applications. Proceedings",

note = "2008 IEEE International Conference on Field Programmable Logic and Applications (FPL'08) ; Conference date: 08-09-2008 Through 10-09-2008",

}

McKeown, M, Woods, R & McAllister, J 2008, Power Efficient DSP Datapath Configuration Methodology for FPGA. in 2008 International Conference on Field Programmable Logic and Applications. Proceedings. pp. 515-518, 2008 IEEE International Conference on Field Programmable Logic and Applications (FPL'08), Heidelberg, Germany, 08/09/2008. https://doi.org/10.1109/FPL.2008.4629997

TY - GEN

T1 - Power Efficient DSP Datapath Configuration Methodology for FPGA

AU - McKeown, Michael

AU - Woods, Roger

AU - McAllister, John

PY - 2008/9

Y1 - 2008/9

N2 - Exploiting the underutilisation of variable-length DSP algorithms during normal operation is vital, when seeking to maximise the achievable functionality of an application within peak power budget. A system level, low power design methodology for FPGA-based, variable length DSP IP cores is presented. Algorithmic commonality is identified and resources mapped with a configurable datapath, to increase achievable functionality. It is applied to a digital receiver application where a 100% increase in operational capacity is achieved in certain modes without significant power or area budget increases. Measured results show resulting architectures requires 19% less peak power, 33% fewer multipliers and 12% fewer slices than existing architectures.

AB - Exploiting the underutilisation of variable-length DSP algorithms during normal operation is vital, when seeking to maximise the achievable functionality of an application within peak power budget. A system level, low power design methodology for FPGA-based, variable length DSP IP cores is presented. Algorithmic commonality is identified and resources mapped with a configurable datapath, to increase achievable functionality. It is applied to a digital receiver application where a 100% increase in operational capacity is achieved in certain modes without significant power or area budget increases. Measured results show resulting architectures requires 19% less peak power, 33% fewer multipliers and 12% fewer slices than existing architectures.

UR - https://www.scopus.com/pages/publications/54949085083

U2 - 10.1109/FPL.2008.4629997

DO - 10.1109/FPL.2008.4629997

M3 - Conference contribution

SN - 978-1-4244-1960-9

SP - 515

EP - 518

BT - 2008 International Conference on Field Programmable Logic and Applications. Proceedings

T2 - 2008 IEEE International Conference on Field Programmable Logic and Applications (FPL'08)

Y2 - 8 September 2008 through 10 September 2008

ER -

Power Efficient DSP Datapath Configuration Methodology for FPGA

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