Power Efficient Dynamic-Range Utilisation for DSP On FPGA

Michael McKeown, Roger Woods, John McAllister

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A power and resource efficient ‘dynamic-range utilisation’ technique to increase operational capacity of DSP IP cores by exploiting redundancy in the data epresentation of sampled analogue input data, is presented. By cleverly partitioning dynamic-range into separable processing threads, several data streams are computed concurrently on the same hardware. Unlike existing techniques which act solely to reduce power consumption due to sign extension, here the dynamic range is exploited to increase operational capacity while still achieving reduced power consumption. This extends an existing system-level, power efficient framework for the design of low power DSP IP cores, which when applied to the design of an FFT IP core in a digital receiver system gives an architecture requiring 50% fewer multipliers, 12% fewer slices and 51%-56% less power.
Original languageEnglish
Title of host publication2008 IEEE Workshop on Signal Processing Systems
Pages233-238
Number of pages6
DOIs
Publication statusPublished - Oct 2008
EventIEEE Workshop on Signal Processing Systems - Washington, Dc, United States
Duration: 01 Oct 200801 Oct 2008

Conference

ConferenceIEEE Workshop on Signal Processing Systems
CountryUnited States
CityWashington, Dc
Period01/10/200801/10/2008

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  • Cite this

    McKeown, M., Woods, R., & McAllister, J. (2008). Power Efficient Dynamic-Range Utilisation for DSP On FPGA. In 2008 IEEE Workshop on Signal Processing Systems (pp. 233-238) https://doi.org/10.1109/SIPS.2008.4671768