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Low-power processors and accelerators that were originally designed for the embedded systems market are emerging as building blocks for servers. Power capping has been actively explored as a technique to reduce the energy footprint of high-performance processors. The opportunities and limitations of power capping on the new low-power processor and accelerator ecosystem are less understood. This paper presents an efficient power capping and management infrastructure for heterogeneous SoCs based on hybrid ARM/FPGA designs. The infrastructure coordinates dynamic voltage and frequency scaling with task allocation on a customised Linux system for the Xilinx Zynq SoC. We present a compiler-assisted power model to guide voltage and frequency scaling, in conjunction with workload allocation between the ARM cores and the FPGA, under given power caps. The model achieves less than 5% estimation bias to mean power consumption. In an FFT case study, the proposed power capping schemes achieve on average 97.5% of the performance of the optimal execution and match the optimal execution in 87.5% of the cases, while always meeting power constraints.
|Title of host publication||Proceedings of the 2014 International Conference on Field-Programmable Technology (FPT)|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Number of pages||4|
|Publication status||Published - Dec 2014|
|Event||13th International Conference on Field-Programmable Technology, FPT 2014 - Shanghai, China|
Duration: 10 Dec 2014 → 12 Dec 2014
|Conference||13th International Conference on Field-Programmable Technology, FPT 2014|
|Period||10/12/2014 → 12/12/2014|
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- 3 Finished
01/08/2012 → 28/04/2017