Pre-Processing Power Traces to Defeat Random Clocking Countermeasures

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)
309 Downloads (Pure)

Abstract

We describe a pre-processing correlation attack on an FPGA implementation of AES, protected with a random clocking countermeasure that exhibits complex variations in both the location and amplitude of the power consumption patterns of the AES rounds. It is demonstrated that the merged round patterns can be pre-processed to identify and extract the individual round amplitudes, enabling a successful power analysis attack. We show that the requirement of the random clocking countermeasure to provide a varying execution time between processing rounds can be exploited to select a sub-set of data where sufficient current decay has occurred, further improving the attack. In comparison with the countermeasure's estimated security of 3 million traces from an integration attack, we show that through application of our proposed techniques that the countermeasure can now be broken with as few as 13k traces.
Original languageEnglish
Title of host publicationIEEE International Symposium on Circuits and Systems (ISCAS), 2015
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages85-88
Number of pages4
ISBN (Electronic)9781479983919
DOIs
Publication statusPublished - 27 May 2015
EventIEEE International Symposium on Circuits and Systems (ISCAS), 2015 - Lisbon, Portugal
Duration: 24 May 201527 May 2015

Conference

ConferenceIEEE International Symposium on Circuits and Systems (ISCAS), 2015
CountryPortugal
CityLisbon
Period24/05/201527/05/2015

Fingerprint

Processing
Field programmable gate arrays (FPGA)
Electric power utilization
Side channel attack

Keywords

  • Power analysis
  • random clocking countermeasure

Cite this

Hodgers, P., Hanley, N., & O'Neill, M. (2015). Pre-Processing Power Traces to Defeat Random Clocking Countermeasures. In IEEE International Symposium on Circuits and Systems (ISCAS), 2015 (pp. 85-88). Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/ISCAS.2015.7168576
Hodgers, Philip ; Hanley, Neil ; O'Neill, Maire. / Pre-Processing Power Traces to Defeat Random Clocking Countermeasures. IEEE International Symposium on Circuits and Systems (ISCAS), 2015 . Institute of Electrical and Electronics Engineers (IEEE), 2015. pp. 85-88
@inproceedings{a51708ef7bd7440d942d4f13c60d4b16,
title = "Pre-Processing Power Traces to Defeat Random Clocking Countermeasures",
abstract = "We describe a pre-processing correlation attack on an FPGA implementation of AES, protected with a random clocking countermeasure that exhibits complex variations in both the location and amplitude of the power consumption patterns of the AES rounds. It is demonstrated that the merged round patterns can be pre-processed to identify and extract the individual round amplitudes, enabling a successful power analysis attack. We show that the requirement of the random clocking countermeasure to provide a varying execution time between processing rounds can be exploited to select a sub-set of data where sufficient current decay has occurred, further improving the attack. In comparison with the countermeasure's estimated security of 3 million traces from an integration attack, we show that through application of our proposed techniques that the countermeasure can now be broken with as few as 13k traces.",
keywords = "Power analysis, random clocking countermeasure",
author = "Philip Hodgers and Neil Hanley and Maire O'Neill",
year = "2015",
month = "5",
day = "27",
doi = "10.1109/ISCAS.2015.7168576",
language = "English",
pages = "85--88",
booktitle = "IEEE International Symposium on Circuits and Systems (ISCAS), 2015",
publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

}

Hodgers, P, Hanley, N & O'Neill, M 2015, Pre-Processing Power Traces to Defeat Random Clocking Countermeasures. in IEEE International Symposium on Circuits and Systems (ISCAS), 2015 . Institute of Electrical and Electronics Engineers (IEEE), pp. 85-88, IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal, 24/05/2015. https://doi.org/10.1109/ISCAS.2015.7168576

Pre-Processing Power Traces to Defeat Random Clocking Countermeasures. / Hodgers, Philip; Hanley, Neil; O'Neill, Maire.

IEEE International Symposium on Circuits and Systems (ISCAS), 2015 . Institute of Electrical and Electronics Engineers (IEEE), 2015. p. 85-88.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Pre-Processing Power Traces to Defeat Random Clocking Countermeasures

AU - Hodgers, Philip

AU - Hanley, Neil

AU - O'Neill, Maire

PY - 2015/5/27

Y1 - 2015/5/27

N2 - We describe a pre-processing correlation attack on an FPGA implementation of AES, protected with a random clocking countermeasure that exhibits complex variations in both the location and amplitude of the power consumption patterns of the AES rounds. It is demonstrated that the merged round patterns can be pre-processed to identify and extract the individual round amplitudes, enabling a successful power analysis attack. We show that the requirement of the random clocking countermeasure to provide a varying execution time between processing rounds can be exploited to select a sub-set of data where sufficient current decay has occurred, further improving the attack. In comparison with the countermeasure's estimated security of 3 million traces from an integration attack, we show that through application of our proposed techniques that the countermeasure can now be broken with as few as 13k traces.

AB - We describe a pre-processing correlation attack on an FPGA implementation of AES, protected with a random clocking countermeasure that exhibits complex variations in both the location and amplitude of the power consumption patterns of the AES rounds. It is demonstrated that the merged round patterns can be pre-processed to identify and extract the individual round amplitudes, enabling a successful power analysis attack. We show that the requirement of the random clocking countermeasure to provide a varying execution time between processing rounds can be exploited to select a sub-set of data where sufficient current decay has occurred, further improving the attack. In comparison with the countermeasure's estimated security of 3 million traces from an integration attack, we show that through application of our proposed techniques that the countermeasure can now be broken with as few as 13k traces.

KW - Power analysis

KW - random clocking countermeasure

U2 - 10.1109/ISCAS.2015.7168576

DO - 10.1109/ISCAS.2015.7168576

M3 - Conference contribution

SP - 85

EP - 88

BT - IEEE International Symposium on Circuits and Systems (ISCAS), 2015

PB - Institute of Electrical and Electronics Engineers (IEEE)

ER -

Hodgers P, Hanley N, O'Neill M. Pre-Processing Power Traces to Defeat Random Clocking Countermeasures. In IEEE International Symposium on Circuits and Systems (ISCAS), 2015 . Institute of Electrical and Electronics Engineers (IEEE). 2015. p. 85-88 https://doi.org/10.1109/ISCAS.2015.7168576