Pre-Processing Power Traces to Defeat Random Clocking Countermeasures

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Abstract

We describe a pre-processing correlation attack on an FPGA implementation of AES, protected with a random clocking countermeasure that exhibits complex variations in both the location and amplitude of the power consumption patterns of the AES rounds. It is demonstrated that the merged round patterns can be pre-processed to identify and extract the individual round amplitudes, enabling a successful power analysis attack. We show that the requirement of the random clocking countermeasure to provide a varying execution time between processing rounds can be exploited to select a sub-set of data where sufficient current decay has occurred, further improving the attack. In comparison with the countermeasure's estimated security of 3 million traces from an integration attack, we show that through application of our proposed techniques that the countermeasure can now be broken with as few as 13k traces.
Original languageEnglish
Title of host publicationIEEE International Symposium on Circuits and Systems (ISCAS), 2015
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages85-88
Number of pages4
ISBN (Electronic)9781479983919
DOIs
Publication statusPublished - 27 May 2015
EventIEEE International Symposium on Circuits and Systems (ISCAS), 2015 - Lisbon, Portugal
Duration: 24 May 201527 May 2015

Conference

ConferenceIEEE International Symposium on Circuits and Systems (ISCAS), 2015
CountryPortugal
CityLisbon
Period24/05/201527/05/2015

Keywords

  • Power analysis
  • random clocking countermeasure

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