Process-variation resilient and voltage-scalable dct architecture for robust low-power computing

G. Karakonstantis, N. Banerjee, K. Roy

Research output: Contribution to journalArticlepeer-review

36 Citations (Scopus)

Abstract

In this paper, we present a novel discrete cosine transform (DCT) architecture that allows aggressive voltage scaling for low-power dissipation, even under process parameter variations with minimal overhead as opposed to existing techniques. Under a scaled supply voltage and/or variations in process parameters, any possible delay errors appear only from the long paths that are designed to be less contributive to output quality. The proposed architecture allows a graceful degradation in the peak SNR (PSNR) under aggressive voltage scaling as well as extreme process variations. Results show that even under large process variations (±3σ around mean threshold voltage) and aggressive supply voltage scaling (at 0.88 V, while the nominal voltage is 1.2 V for a 90-nm technology), there is a gradual degradation of image quality with considerable power savings (71% at PSNR of 23.4 dB) for the proposed architecture, when compared to existing implementations in a 90-nm process technology.
Original languageEnglish
Pages (from-to)1461-1470
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume18
Issue number10
DOIs
Publication statusPublished - 01 Oct 2010

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