There is an increasing demand for high performance image processing platforms based on field programmable gate array (FPGA). The Histogram of Orientated Gradients (HOG) algorithm is a feature descriptor algorithm used in object detection for many security applications. The chapter examines the implementation of this key algorithm using an FPGA-based soft-core architecture approach. Firstly, the HOG algorithm is described and its performance profiled from a computation and bandwidth perspective. Then the IPPro soft-core processor architecture is introduced and a number of mapping strategies are covered. A HOG implementation is demonstrated on a Zynq platform, resulting in a design operating at 15.36 fps; this compares favorably with the performance and resources of handcrafted VHDL code.
Kelly, C., Woods, R., Amiri, M., Siddiqui, F. M., & Rafferty, K. (2019). Programmable Architectures for Histogram of Oriented Gradients Processing. In Handbook of Signal Processing Systems (pp. 649 - 682). Springer. https://doi.org/10.1007/978-3-319-91734-4_18