Programmable architectures for histogram of oriented gradients processing

Colm Kelly; Roger Woods; Moslem Amiri; Fahad Manzoor Siddiqui; Karen Rafferty

doi:10.1007/978-3-319-91734-4_18

Programmable architectures for histogram of oriented gradients processing

Colm Kelly, Roger Woods, Moslem Amiri, Fahad Manzoor Siddiqui, Karen Rafferty

School of Electronics, Electrical Engineering and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Chapter (peer-reviewed) › peer-review

Abstract

There is an increasing demand for high performance image processing platforms based on field programmable gate array (FPGA). The Histogram of Orientated Gradients (HOG) algorithm is a feature descriptor algorithm used in object detection for many security applications. The chapter examines the implementation of this key algorithm using an FPGA-based soft-core architecture approach. Firstly, the HOG algorithm is described and its performance profiled from a computation and bandwidth perspective. Then the IPPro soft-core processor architecture is introduced and a number of mapping strategies are covered. A HOG implementation is demonstrated on a Zynq platform, resulting in a design operating at 15.36 fps; this compares favorably with the performance and resources of handcrafted VHDL code.

Original language	English
Title of host publication	Handbook of Signal Processing Systems
Publisher	Springer
Pages	649 - 682
Number of pages	33
ISBN (Electronic)	978-3-319-91734-4
DOIs	https://doi.org/10.1007/978-3-319-91734-4_18
Publication status	Published - 2019

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10.1007/978-3-319-91734-4_18

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@inbook{f4573899ab4f4679bd5bf3197ce87d37,

title = "Programmable architectures for histogram of oriented gradients processing",

abstract = "There is an increasing demand for high performance image processing platforms based on field programmable gate array (FPGA). The Histogram of Orientated Gradients (HOG) algorithm is a feature descriptor algorithm used in object detection for many security applications. The chapter examines the implementation of this key algorithm using an FPGA-based soft-core architecture approach. Firstly, the HOG algorithm is described and its performance profiled from a computation and bandwidth perspective. Then the IPPro soft-core processor architecture is introduced and a number of mapping strategies are covered. A HOG implementation is demonstrated on a Zynq platform, resulting in a design operating at 15.36 fps; this compares favorably with the performance and resources of handcrafted VHDL code.",

author = "Colm Kelly and Roger Woods and Moslem Amiri and Siddiqui, {Fahad Manzoor} and Karen Rafferty",

year = "2019",

doi = "10.1007/978-3-319-91734-4_18",

language = "English",

pages = "649 -- 682",

booktitle = "Handbook of Signal Processing Systems",

publisher = "Springer",

}

TY - CHAP

T1 - Programmable architectures for histogram of oriented gradients processing

AU - Kelly, Colm

AU - Woods, Roger

AU - Amiri, Moslem

AU - Siddiqui, Fahad Manzoor

AU - Rafferty, Karen

PY - 2019

Y1 - 2019

N2 - There is an increasing demand for high performance image processing platforms based on field programmable gate array (FPGA). The Histogram of Orientated Gradients (HOG) algorithm is a feature descriptor algorithm used in object detection for many security applications. The chapter examines the implementation of this key algorithm using an FPGA-based soft-core architecture approach. Firstly, the HOG algorithm is described and its performance profiled from a computation and bandwidth perspective. Then the IPPro soft-core processor architecture is introduced and a number of mapping strategies are covered. A HOG implementation is demonstrated on a Zynq platform, resulting in a design operating at 15.36 fps; this compares favorably with the performance and resources of handcrafted VHDL code.

AB - There is an increasing demand for high performance image processing platforms based on field programmable gate array (FPGA). The Histogram of Orientated Gradients (HOG) algorithm is a feature descriptor algorithm used in object detection for many security applications. The chapter examines the implementation of this key algorithm using an FPGA-based soft-core architecture approach. Firstly, the HOG algorithm is described and its performance profiled from a computation and bandwidth perspective. Then the IPPro soft-core processor architecture is introduced and a number of mapping strategies are covered. A HOG implementation is demonstrated on a Zynq platform, resulting in a design operating at 15.36 fps; this compares favorably with the performance and resources of handcrafted VHDL code.

UR - https://www.springer.com/gp/book/9783319917337#aboutBook

U2 - 10.1007/978-3-319-91734-4_18

DO - 10.1007/978-3-319-91734-4_18

M3 - Chapter (peer-reviewed)

SP - 649

EP - 682

BT - Handbook of Signal Processing Systems

PB - Springer

ER -

Programmable architectures for histogram of oriented gradients processing

Abstract

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FPGA soft-core processors, compiler and hardware optimizations validated using HOG

FPGA soft-core processors, compiler and hardware optimizations validated using HOG

Histogram of oriented gradients front end processing: an FPGA based processor approach

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