Programmable high-performance IIR filter chip

R.F. Woods, G. Floyd, K. Wood, R. Evans, J.V. McCanny

Research output: Contribution to journalArticlepeer-review

4 Citations (Scopus)

Abstract

The paper presents a state-of-the-art commercial demonstrator chip for infinite impulse response (IIR) filtering. The programmable IIR filter chip contains eight multiplier/accumulators that can be configured in one of five different modes to implement up to a 16th-order IIR filter. The multiply-accumulate block is based on a highly regular systolic array architecture and uses a redundant number system to overcome problems of pipelining in the feedback loop. The chip has been designed using the GEC Plessey Semiconductors CLA 78000 series gate array, operates on 16-bit two's complement data and has a clock speed of 30 MHz. Issues such as overflow detection and design for testability have also been addressed and are described.
Original languageEnglish
Pages (from-to)179-185
Number of pages7
JournalIEE Proceedings - Circuits, Devices and Systems
Volume142
Issue number3
DOIs
Publication statusPublished - 01 Jun 1995

Bibliographical note

Copyright 2004 Elsevier B.V., All rights reserved.

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