This paper presents the design of a single chip adaptive beamformer which contains 5 million transistors and can perform 50 GigaFlops. The core processor of the adaptive beamformer is a QR-array processor implemented on a fully efficient linear systolic architecture. The paper highlights a number of rapid design techniques that have been used to realize the design. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilization of a library of parameterizable silicon intellectual property (IP) cores, to rapidly develop the circuit layouts.
|Title of host publication||“Signal Processing Systems - Design and Implementation, SiPS 98”, IEEE Signal Processing Society/IEEE Circuits and Systems Society Press eds E Manolakos, A. Chandrakasan, L G Chen, W Burleson, K Konstantinides|
|Number of pages||10|
|ISBN (Electronic)||ISBN 0-7803-4997-0/98|
|Publication status||Published - 01 Jan 1998|