Methods are presented for developing synthesizable FFT cores. These are based on a modular approach in which parameterized commutator and processor blocks are cascaded to implement the computations required in many important FFT signal flow graphs. In addition, it is shown how the use of a digital serial data organization can be used to produce systems that offer 100% processor utilization along with reductions in storage requirements. The approach has been used to create generators for the automated synthesis of FFT cores that are portable across a broad range of silicon technologies. Resulting chip designs are competitive with ones created using manual methods but with significant reductions in design times.
|Number of pages||11|
|Journal||IEEE Transactions on Signal Processing|
|Publication status||Published - 01 Jan 1999|
Bibliographical noteCopyright 2012 Elsevier B.V., All rights reserved.
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Signal Processing