Rapid design of discrete orthonormal wavelet transforms using silicon IP components

S Masud*, JV McCanny

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A rapid design methodology for orthonormal wavelet transform cores has been developed. This methodology is based on a generic, scaleable architecture utilising time-interleaved coefficients for the wavelet transform filters. The architecture has been captured in VHDL and parameterised in terms of wavelet family, wavelet type, data word length and coefficient word length. The control circuit is embedded within the cores and allows them to be cascaded without any interface glue logic for any desired level of decomposition. Case studies for stand alone and cascaded silicon cores for single and multi-stage wavelet analysis respectively are reported. The design time to produce silicon layout of a wavelet based system has been reduced to typically less than a day. The cores are comparable in area and performance to handcrafted designs. The designs are portable across a range of foundries and are also applicable to FPGA and PLD implementations.

Original languageEnglish
Title of host publicationICASSP '99: 1999 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, PROCEEDINGS VOLS I-VI
Place of PublicationNEW YORK
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages2167-2170
Number of pages4
ISBN (Print)0-7803-5041-3
Publication statusPublished - 1999
EventIEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 99) - Phoenix, United States
Duration: 15 Mar 199919 Mar 1999

Publication series

NameInternational Conference on Acoustics Speech and Signal Processing (ICASSP)
PublisherIEEE
ISSN (Print)1520-6149

Conference

ConferenceIEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 99)
CountryUnited States
CityPhoenix
Period15/03/199919/03/1999

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