Rapid design of DSP ASIC cores using hierarchical VHDL libraries

J.V. McCanny; Y. Hu; T.J. Ding; D. Trainor; D. Ridge

doi:10.1109/ACSSC.1996.599167

Rapid design of DSP ASIC cores using hierarchical VHDL libraries

J.V. McCanny, Y. Hu, T.J. Ding, D. Trainor, D. Ridge

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

Methods are presented for the rapid design of DSP ASICs based on the use of a series of hierarchical VHDL libraries which are portable across many silicon foundries. These allows complex DSP silicon systems to be developed in a small fraction of the time normally required. Resulting designs are highly competitive with those developed using more conventional methods. The approach is illustrated using several examples. These include ADPCM codecs, as well as DCT and FFT cores.

Original language	English
Title of host publication	Conference record of the 30th Asilomar Conference of Signals, Systems and Computers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1344-1348
Number of pages	5
Volume	2
ISBN (Print)	0-8186-7646-9
DOIs	https://doi.org/10.1109/ACSSC.1996.599167
Publication status	Published - 01 Jan 1997

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10.1109/ACSSC.1996.599167

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abstract = "Methods are presented for the rapid design of DSP ASICs based on the use of a series of hierarchical VHDL libraries which are portable across many silicon foundries. These allows complex DSP silicon systems to be developed in a small fraction of the time normally required. Resulting designs are highly competitive with those developed using more conventional methods. The approach is illustrated using several examples. These include ADPCM codecs, as well as DCT and FFT cores.",

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AB - Methods are presented for the rapid design of DSP ASICs based on the use of a series of hierarchical VHDL libraries which are portable across many silicon foundries. These allows complex DSP silicon systems to be developed in a small fraction of the time normally required. Resulting designs are highly competitive with those developed using more conventional methods. The approach is illustrated using several examples. These include ADPCM codecs, as well as DCT and FFT cores.

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ER -

Rapid design of DSP ASIC cores using hierarchical VHDL libraries

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