Rapid design of DSP ASIC cores using hierarchical VHDL libraries

J.V. McCanny, Y. Hu, T.J. Ding, D. Trainor, D. Ridge

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Methods are presented for the rapid design of DSP ASICs based on the use of a series of hierarchical VHDL libraries which are portable across many silicon foundries. These allows complex DSP silicon systems to be developed in a small fraction of the time normally required. Resulting designs are highly competitive with those developed using more conventional methods. The approach is illustrated using several examples. These include ADPCM codecs, as well as DCT and FFT cores.
Original languageEnglish
Title of host publicationConference record of the 30th Asilomar Conference of Signals, Systems and Computers
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages1344-1348
Number of pages5
Volume2
ISBN (Print)0-8186-7646-9
DOIs
Publication statusPublished - 01 Jan 1997

Bibliographical note

Copyright 2004 Elsevier Science B.V., Amsterdam. All rights reserved.

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