Rapid design of high performance adaptive equalizer and Viterbi decoder for the class-IV PRML channel

B. D.E. Smith*, J. V. Mc Canny

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

1 Citation (Scopus)

Abstract

Methods for the rapid design and VLSI implementation of two key components of the class-IV partial response maximum likelihood channel (PR-IV), the adaptive filter and the Viterbi decoder, are described. These are implemented using parameterized modules, constructed from a synthesizable silicon architecture library containing core DSP and arithmetic functions. Design studies, based on a 0.35 micron 3.3 V standard cell CMOS process, indicate that worst case sampling rates of 180 mega-samples per second are achievable with a power consumption of 0.8 W and an area of 4.3 mm2. Higher sampling rates can be obtained by operating a number of filter modules in parallel. This approach offers power saving advantages when compared with systems employing pipelined filters operating at the same speed.

Original languageEnglish
Pages307-316
Number of pages10
Publication statusPublished - 01 Jan 1998
EventProceedings of the 1998 IEEE Workshop on Signal Processing Systems, SIPS - Cambridge, United States
Duration: 08 Oct 199810 Oct 1998

Conference

ConferenceProceedings of the 1998 IEEE Workshop on Signal Processing Systems, SIPS
CountryUnited States
CityCambridge
Period08/10/199810/10/1998

ASJC Scopus subject areas

  • Signal Processing
  • Media Technology

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