@inproceedings{0bbd2663be9341558cfb51e708f446b5,
title = "Rapid design of high performance adaptive equalizer and Viterbi decoder for the class-IV PRML channel",
abstract = "Methods for the rapid design and VLSI implementation of two key components of the class-IV partial response maximum likelihood channel (PR-IV), the adaptive filter and the Viterbi decoder, are described. These are implemented using parameterized modules, constructed from a synthesizable silicon architecture library containing core DSP and arithmetic functions. Design studies, based on a 0.35 micron 3.3 V standard cell CMOS process, indicate that worst case sampling rates of 180 mega-samples per second are achievable with a power consumption of 0.8 W and an area of 4.3 mm2. Higher sampling rates can be obtained by operating a number of filter modules in parallel. This approach offers power saving advantages when compared with systems employing pipelined filters operating at the same speed.",
author = "Smith, {B. D.E.} and {Mc Canny}, {J. V.}",
year = "1998",
month = jan,
day = "1",
doi = "10.1109/SIPS.1998.715793",
language = "English",
isbn = "0-7803-4997-0",
series = "IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation: Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "307--316",
booktitle = "1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation: Proceedings",
address = "United States",
note = "1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation ; Conference date: 10-10-1998 Through 10-10-1998",
}