A methodology has been developed which allows a non-specialist to rapidly design silicon wavelet transform cores for a variety of specifications. The cores include both forward and inverse orthonormal wavelet transforms. This methodology is based on efficient, modular and scaleable architectures utilising time-interleaved coefficients for the wavelet transform filters. The cores are parameterized in terms of wavelet type and data and coefficient word lengths. The designs have been captured in VHDL and are hence portable across a range of silicon foundries as well as FPGA and PLD implementations.
|Number of pages||7|
|Journal||IEE Colloquium (Digest)|
|Publication status||Published - 16 Sep 1999|
Bibliographical noteCopyright 2008 Elsevier B.V., All rights reserved.
ASJC Scopus subject areas
- Electrical and Electronic Engineering