Abstract
We present RC4-AccSuite, a hardware accelerator, which combines the flexibility of an application specific instruction set processor and the performance of an application specific IC for the most widely deployed commercial stream cipher RC4 and its eight prominent variants, including Spritz (CRYPTO-2014 Rump-session). Our carefully designed instruction set architecture reuses combinational and sequential logic at its various pipeline stages and memories, saving up to 41% in terms of area, compared with the individual cores, while the power budget being dictated primarily by the variant used. Moreover, using state replication, noticeable throughput performance enhancement in RC4 variants is achieved. RC4-AccSuite possesses extensibility for future variants of RC4 with little or no tweaking.
Original language | English |
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Pages (from-to) | 1072-1084 |
Number of pages | 13 |
Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Volume | 25 |
Issue number | 3 |
Early online date | 27 Sep 2016 |
Publication status | Published - Mar 2017 |
Keywords
- Application specific IC (ASIC)
- application specific instruction set processor (ASIP)
- hardware accelerator
- high throughput
- RC4
- stream cipher
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering