Reconfigurable Architectures for Network Processing

Research output: Chapter in Book/Report/Conference proceedingOther chapter contribution

Abstract

An overview of research on reconfigurable architectures for network processing applications within the Institute of Electronics, Communications and Information Technology (ECIT) is presented. Three key network processing topics, namely node throughput, Quality of Service (QoS) and security are examined where custom reconfigurability allows network nodes to adapt to fluctuating network traffic and customer demands. Various architectural possibilities have been investigated in order to explore the options and tradeoffs available when using reconfigurability for packet/frame processing, packet-scheduling and data encryption/decryption. This research has shown there is no common approach that can be applied. Rather the methodologies used and the cost-benefits for incorporation of reconfigurability depend on each of the functions considered, for example being well suited to encryption/decryption but not packet/frame processing. © 2005 IEEE.
Original languageEnglish
Title of host publication2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
Pages75-83
Number of pages9
Volume2005
DOIs
Publication statusPublished - Apr 2005
EventIEEE International Symposium on VLSI Technology Systems and Applications (VLSI-TSA) - Taiwan, Taiwan, Province of China
Duration: 01 Apr 200501 Apr 2005

Conference

ConferenceIEEE International Symposium on VLSI Technology Systems and Applications (VLSI-TSA)
CountryTaiwan, Province of China
CityTaiwan
Period01/04/200501/04/2005

Bibliographical note

ISSN: 0780390601

ASJC Scopus subject areas

  • Engineering(all)

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