A new domain-specific, reconfigurable system-on-a-chip (SoC) architecture is proposed for video motion estimation. This has been designed to cover most of the common block-based video coding standards, including MPEG-2, MPEG-4, H.264, WMV-9 and AVS. The architecture exhibits simple control, high throughput and relatively low hardware cost when compared with existing circuits. It can also easily handle flexible search ranges without any increase in silicon area and can be configured prior to the start of the motion estimation process for a specific standard. The computational rates achieved make the circuit suitable for high-end video processing applications, such as HDTV. Silicon design studies indicate that circuits based on this approach incur only a relatively small penalty in terms of power dissipation and silicon area when compared with implementations for specific standards. Indeed, the cost/performance achieved exceeds that of existing but specific solutions and greatly exceeds that of general purpose field programmable gate array (FPGA) designs.
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
Lu, L., McCanny, J., & Sezer, S. (2010). Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding. IET Computers And Digital Techniques, 4(5), 349-364. [ICDTA6000004000005000349000001]. https://doi.org/10.1049/iet-cdt.2008.0106