Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder

Pascal Meinerzhagen; Andrea Bonetti; Georgios Karakonstantis; Christoph Roth; Frank Giirkaynak; Andreas Burg

doi:10.1109/ISCAS.2015.7168911

Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder

Pascal Meinerzhagen, Andrea Bonetti, Georgios Karakonstantis, Christoph Roth, Frank Giirkaynak, Andreas Burg

School of Electronics, Electrical Engineering and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

The area and power consumption of low-density parity check (LDPC) decoders are typically dominated by embedded memories. To alleviate such high memory costs, this paper exploits the fact that all internal memories of a LDPC decoder are frequently updated with new data. These unique memory access statistics are taken advantage of by replacing all static standard-cell based memories (SCMs) of a prior-art LDPC decoder implementation by dynamic SCMs (D-SCMs), which are designed to retain data just long enough to guarantee reliable operation. The use of D-SCMs leads to a 44% reduction in silicon area of the LDPC decoder compared to the use of static SCMs. The low-power LDPC decoder architecture with refresh-free D-SCMs was implemented in a 90nm CMOS process, and silicon measurements show full functionality and an information bit throughput of up to 600 Mbps (as required by the IEEE 802.11n standard).

Original language	English
Title of host publication	Proceedings - IEEE International Symposium on Circuits and Systems
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1426-1429
Number of pages	4
ISBN (Print)	9781479983919, ISSN: 0271 4310
DOIs	https://doi.org/10.1109/ISCAS.2015.7168911
Publication status	Published - 27 Jul 2015
Event	IEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal Duration: 24 May 2015 → 27 May 2015

Conference

Conference	IEEE International Symposium on Circuits and Systems, ISCAS 2015
Country/Territory	Portugal
City	Lisbon
Period	24/05/2015 → 27/05/2015

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2015.7168911

Cite this

Meinerzhagen, P., Bonetti, A., Karakonstantis, G., Roth, C., Giirkaynak, F., & Burg, A. (2015). Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 1426-1429). Article 7168911 Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2015.7168911

@inproceedings{73d825eb09d240f0b0e4be8b7cf1ff14,

title = "Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder",

abstract = "The area and power consumption of low-density parity check (LDPC) decoders are typically dominated by embedded memories. To alleviate such high memory costs, this paper exploits the fact that all internal memories of a LDPC decoder are frequently updated with new data. These unique memory access statistics are taken advantage of by replacing all static standard-cell based memories (SCMs) of a prior-art LDPC decoder implementation by dynamic SCMs (D-SCMs), which are designed to retain data just long enough to guarantee reliable operation. The use of D-SCMs leads to a 44% reduction in silicon area of the LDPC decoder compared to the use of static SCMs. The low-power LDPC decoder architecture with refresh-free D-SCMs was implemented in a 90nm CMOS process, and silicon measurements show full functionality and an information bit throughput of up to 600 Mbps (as required by the IEEE 802.11n standard).",

author = "Pascal Meinerzhagen and Andrea Bonetti and Georgios Karakonstantis and Christoph Roth and Frank Giirkaynak and Andreas Burg",

year = "2015",

month = jul,

day = "27",

doi = "10.1109/ISCAS.2015.7168911",

language = "English",

isbn = "9781479983919",

pages = "1426--1429",

booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "IEEE International Symposium on Circuits and Systems, ISCAS 2015 ; Conference date: 24-05-2015 Through 27-05-2015",

}

Meinerzhagen, P, Bonetti, A, Karakonstantis, G, Roth, C, Giirkaynak, F & Burg, A 2015, Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder. in Proceedings - IEEE International Symposium on Circuits and Systems., 7168911, Institute of Electrical and Electronics Engineers Inc., pp. 1426-1429, IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, 24/05/2015. https://doi.org/10.1109/ISCAS.2015.7168911

Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder. / Meinerzhagen, Pascal; Bonetti, Andrea; Karakonstantis, Georgios et al.
Proceedings - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 2015. p. 1426-1429 7168911.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder

AU - Meinerzhagen, Pascal

AU - Bonetti, Andrea

AU - Karakonstantis, Georgios

AU - Roth, Christoph

AU - Giirkaynak, Frank

AU - Burg, Andreas

PY - 2015/7/27

Y1 - 2015/7/27

N2 - The area and power consumption of low-density parity check (LDPC) decoders are typically dominated by embedded memories. To alleviate such high memory costs, this paper exploits the fact that all internal memories of a LDPC decoder are frequently updated with new data. These unique memory access statistics are taken advantage of by replacing all static standard-cell based memories (SCMs) of a prior-art LDPC decoder implementation by dynamic SCMs (D-SCMs), which are designed to retain data just long enough to guarantee reliable operation. The use of D-SCMs leads to a 44% reduction in silicon area of the LDPC decoder compared to the use of static SCMs. The low-power LDPC decoder architecture with refresh-free D-SCMs was implemented in a 90nm CMOS process, and silicon measurements show full functionality and an information bit throughput of up to 600 Mbps (as required by the IEEE 802.11n standard).

AB - The area and power consumption of low-density parity check (LDPC) decoders are typically dominated by embedded memories. To alleviate such high memory costs, this paper exploits the fact that all internal memories of a LDPC decoder are frequently updated with new data. These unique memory access statistics are taken advantage of by replacing all static standard-cell based memories (SCMs) of a prior-art LDPC decoder implementation by dynamic SCMs (D-SCMs), which are designed to retain data just long enough to guarantee reliable operation. The use of D-SCMs leads to a 44% reduction in silicon area of the LDPC decoder compared to the use of static SCMs. The low-power LDPC decoder architecture with refresh-free D-SCMs was implemented in a 90nm CMOS process, and silicon measurements show full functionality and an information bit throughput of up to 600 Mbps (as required by the IEEE 802.11n standard).

UR - http://www.scopus.com/inward/record.url?scp=84946223844&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2015.7168911

DO - 10.1109/ISCAS.2015.7168911

M3 - Conference contribution

AN - SCOPUS:84946223844

SN - 9781479983919

SN - ISSN: 0271 4310

SP - 1426

EP - 1429

BT - Proceedings - IEEE International Symposium on Circuits and Systems

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE International Symposium on Circuits and Systems, ISCAS 2015

Y2 - 24 May 2015 through 27 May 2015

ER -

Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder

Abstract

Conference

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this