The main memory in today’s systems is based on DRAMs, which may offer low cost and high density storage for large amounts of data but it comes with a main drawback; DRAM cells need to be refreshed frequently for retaining the stored data. The refresh rate in modern DRAMs is set based on the worst-case retention time without considering access statistics, thereby resulting in very frequent refresh operations. Such high refresh rate leads eventually to large power and performance overheads, which are increasing with higher DRAM densities. However, such high refresh rates may not even required due to extremely low probability of the actual occurrence of the assumed worst-case scenarios, or due to the implicit refresh operation that occur during every memory access, a feature that has not been yet been studied in depth. In this paper, we enhance the state-of-the-art by systematically exploiting the implicit refresh of memory access for relaxing the refresh rate, while minimizing the resulting memory errors. This is achieved by modifying the algorithmic parameters that influence the access patterns such that all stored data are being touched within a target time interval that is necessary for meeting a target error rate. The proposed method is applied to stencil-based algorithms which represent a wide class of algorithms used in numerical analysis, image processing and cellular automata applications. The efficacy of the proposed method is demonstrated on an off-the-shelf server running a fully fledged Linux OS and results show that it is even possible to completely disable DRAM refresh with minor quality loss.
|Title of host publication||23rd IEEE International Symposium on On-Line Testing and Robust System Design 2017: Proceedings|
|Publication status||Published - 21 Sep 2017|
|Event||23rd IEEE International Symposium on On-Line Testing and Robust System Design - Hotel Makedonia Palace, Thessaloniki, Greece|
Duration: 03 Jul 2017 → 05 Jul 2017
|Conference||23rd IEEE International Symposium on On-Line Testing and Robust System Design|
|Period||03/07/2017 → 05/07/2017|
Tovletoglou, K., Nikolopoulos, D. S., & Karakonstantis, G. (2017). Relaxing DRAM Refresh Rate through Access Pattern Scheduling: A Case Study on Stencil-based Algorithms. In 23rd IEEE International Symposium on On-Line Testing and Robust System Design 2017: Proceedings (pp. 1-6) https://doi.org/10.1109/IOLTS.2017.8046197