Cryptographic co-processors are integral to the modern System-on-Chips. Flexibility in such designs serves dual purpose, i.e., it enables acceleration of different essential cryptographic primitives (Encryption/Authentication/Pseudo Random Number Generation (PRNG)) and also results in design compaction via resource sharing. In this context, a novel resource-shared crypto-coprocessor, named AEHA−3ispresented,whichcombinestwoNationalInstituteofStandardsandTechnology(NIST)standardizedalgorithms,i.e.,AdvanceEncryptionStandard(AES)andSecureHashAlgorithm−3(SHA−3).Duetoalgorithmicdissimilarities,sofarnoresource−sharedimplementationenablingAESkeyscheduling/enc/decandSHA−3hasbeenpresented.AEHA-3 exploits resource-sharing for area reduction, i.e., integration of Look-Up-Tables (I-Tables) for AES enc/dec; logical optimization of Six Input Equation (SixIE) for SHA-3; a Unified XOR Section to carry out both key whitening in AES and SHA-3 transformations. Furthermore, the AES key scheduling was performed using the same resource-shared hardware. The proposed AE$HA-3 on Xilinx Virtex FPGA family results in highest hardware efficiency in terms of Throughput per Slice (TPS), along with a 49.37% area consumption reduction, when compared against the smallest stand-alone implementations presented to date.
|Number of pages||14|
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|Early online date||03 Jun 2020|
|Publication status||Early online date - 03 Jun 2020|