Reverse converter design via parallel-prefix adders: novel components, methodology, and implementations

Azadeh Alsadat Emrani Zarandi, Amir Sabbagh Molahosseini*, Saeid Sorouri, Mehdi Hosseinzadeh, Samuel Antão, Leonel Sousa

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

19 Citations (Scopus)

Abstract

In this brief, the implementation of residue number system reverse converters based on well-known regular and modular parallel-prefix adders is analyzed. The VLSI implementation results show a significant delay reduction and area × time 2 improvements, all this at the cost of higher power consumption, which is the main reason preventing the use of parallel-prefix adders to achieve high-speed reverse converters in nowadays systems. Hence, to solve the high power consumption problem, novel specific hybrid parallel-prefix-based adder components that provide better tradeoff between delay and power consumption are herein presented to design reverse converters. A methodology is also described to design reverse converters based on different kinds of prefix adders. This methodology helps the designer to adjust the performance of the reverse converter based on the target application and existing constraints.
Original languageEnglish
Pages (from-to)374 - 378
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume23
Issue number2
Early online date26 Feb 2014
DOIs
Publication statusPublished - Feb 2015
Externally publishedYes

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