Abstract
The continuous scaling of transistor sizes and the increased
parametric variations render nanometer circuits more prone to timing
failures. To protect circuits from such failures, typically designers adopt
pessimistic timing margins, which are estimated under rare worst-case
conditions. In this paper, we present a technique that mitigates such
pessimistic margins by minimizing the number of timing failures. In
particular, we propose a method that minimizes the number of long
latency paths within each processor pipeline stage and constraints
them in as few stages as possible. Such a method allows us not only
to reduce the timing failures, but also to limit the potential errorprone locations to only few pipeline stages. To further reduce these
failures, we exploit the path excitation dependence on data patterns
and truncate the bitwidth of the operands in the few remaining long
latency paths by setting a number of less significant bits (LSBs) to
a constant value of zero. Such a truncation may incur quality loss,
but this is limited since it is applied only to the LSBs of the few
operands that may activate the confined error-prone long latency paths.
To evaluate the efficiency of our method, we perform post-place and
route dynamic timing analysis based on real operands extracted from
a variety of applications. This helps to estimate the bit error rate,
while considering the data dependent path excitation. When applied to
an IEEE-754 compatible double precision Floating Point Unit (FPU),
the proposed approach reduces the timing failures by 216.25× on
average compared to the reference FPU design under an assumed 8.1%
variation-induced worst-case path delay increase in a 45 nm process.
Our results show that the path shaping alone introduces a negligible
0.25% area and 5.7% power overheads with no performance cost. Finally,
we demonstrate that by combining the path shaping with aggressive
operand bitwidth truncation, we enable power savings of up-to 44.7%
due to the substantially reduced switching activity at minimal quality loss.
Original language | English |
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Pages (from-to) | 25-36 |
Number of pages | 12 |
Journal | IEEE Transactions on Device and Materials Reliability |
Volume | 19 |
Issue number | 1 |
DOIs | |
Publication status | Published - 12 Feb 2019 |
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Dive into the research topics of 'Significance-Driven Data Truncation for Preventing Timing Failures'. Together they form a unique fingerprint.Student theses
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Cross-layer instruction-aware timing error mitigation & evaluation for energy-efficient dependable architectures
Tsiokanos, I. (Author), Karakonstantis, G. (Supervisor), Woods, R. (Supervisor) & Nikolopoulos, D. S. (Supervisor), Jul 2021Student thesis: Doctoral Thesis › Doctor of Philosophy
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