Single-chip FPGA implementation of the advanced encryption standard algorithm

Research output: Chapter in Book/Report/Conference proceedingConference contribution

19 Citations (Scopus)

Abstract

A single-chip FPGA implementation of the new Advanced Encryption Standard (AES) algorithm, Rijndael is presented. Field Programmable Gate Arrays (FPGAs) are well suited to encryption implementations due to their flexibility and an architecture, which can be exploited to accommodate typical encryption transformations. The FPGA implementation described here is that of a fully pipelined single-chip Rijndael design which runs at a data rate of 7 Gbits/sec on a Xilinx Virtex-E XCV812E-8-BG560 FPGA device. This proves to be one of the fastest single-chip FPGA Rijndael implementations currently available. The high Block RAM content of the Virtex-E device is exploited in the design.

Original languageEnglish
Title of host publicationField-Programmable Logic and Applications - 11th International Conference, FPL 2001, Proceedings
PublisherSpringer-Verlag
Pages152-161
Number of pages10
ISBN (Print)3540424997, 9783540424994
Publication statusPublished - 01 Jan 2001
Event11th International Conference on Field-Programmable Logic and Applications, FPL 2001 - Belfast, United Kingdom
Duration: 27 Aug 200129 Aug 2001

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume2147
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference11th International Conference on Field-Programmable Logic and Applications, FPL 2001
CountryUnited Kingdom
CityBelfast
Period27/08/200129/08/2001

Keywords

  • AES
  • Encryption
  • FPGA Implementation
  • Rijndael

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

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