Abstract
Soft IP cores can be realized as parameterisable HDL descriptions of circuit architecture where the performance comes from efficiently mapping system functionality. However, special arithmetic operations e.g. division, reciprocal, can restrict this mapping. An approach is presented that maps the system onto foundation operations, multiplication and additioa thereby giving a freer mapping of the full system. The methodology and results are given for a QR-based recursive least squares filter design on a Xilinx Virtex 4 FPGA giving a 5 GFLOPS performance.
Original language | English |
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Title of host publication | Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL |
Pages | 597-600 |
Number of pages | 4 |
DOIs | |
Publication status | Published - 01 Dec 2007 |
Externally published | Yes |
Event | 2007 International Conference on Field Programmable Logic and Applications, FPL - Amsterdam, Netherlands Duration: 27 Aug 2007 → 29 Aug 2007 |
Conference
Conference | 2007 International Conference on Field Programmable Logic and Applications, FPL |
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Country/Territory | Netherlands |
City | Amsterdam |
Period | 27/08/2007 → 29/08/2007 |
ASJC Scopus subject areas
- Computer Science Applications
- Electrical and Electronic Engineering