Soft IP core implementation of recursive least squares filter using only multplicative and additive operators

Gaye Lightbody*, Roger Woods, Jonathan Francey

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

Soft IP cores can be realized as parameterisable HDL descriptions of circuit architecture where the performance comes from efficiently mapping system functionality. However, special arithmetic operations e.g. division, reciprocal, can restrict this mapping. An approach is presented that maps the system onto foundation operations, multiplication and additioa thereby giving a freer mapping of the full system. The methodology and results are given for a QR-based recursive least squares filter design on a Xilinx Virtex 4 FPGA giving a 5 GFLOPS performance.

Original languageEnglish
Title of host publicationProceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL
Pages597-600
Number of pages4
DOIs
Publication statusPublished - 01 Dec 2007
Externally publishedYes
Event2007 International Conference on Field Programmable Logic and Applications, FPL - Amsterdam, Netherlands
Duration: 27 Aug 200729 Aug 2007

Conference

Conference2007 International Conference on Field Programmable Logic and Applications, FPL
Country/TerritoryNetherlands
CityAmsterdam
Period27/08/200729/08/2007

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering

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