Source/drain extension region engineering in FinFETs for low-voltage analog applications

Abhinav Kranti, Alastair Armstrong

Research output: Contribution to journalArticlepeer-review

70 Citations (Scopus)


In this letter, we propose a novel design methodology for engineering source/drain extension (SDE) regions to simultaneously improve intrinsic dc gain (A(vo)) and cutoff frequency (f(T)) of 25-nm gate-length FinFETs operated at low drain-current (I-ds = 10 mu A/mu m). SDE region optimization in 25-nm FinFETs results in exceptionally high values of Avo (similar to 45 dB) and f(T) (similar to 70 GHz), which is nearly 2.5 times greater when compared to devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient, and the spacer-to-gradient ratio on key analog figures of merit is examined in detail. This letter provides new opportunities for realizing future low-voltage/low-power analog design with nanoscale SDE-engineered FinFETs.
Original languageEnglish
Pages (from-to)139-141
Number of pages3
JournalIEEE Electron Device Letters
Issue number2
Publication statusPublished - Feb 2007

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


Dive into the research topics of 'Source/drain extension region engineering in FinFETs for low-voltage analog applications'. Together they form a unique fingerprint.

Cite this