Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Jeremy Constantin, Zheng Wang, Georgios Karakonstantis, Andreas Burg, Anupam Chattopadhyay

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)
217 Downloads (Pure)


This paper proposes a novel approach to modeling of gate level timing errors during high-level instruction set simula- tion. In contrast to conventional, purely random fault injec- tion, our physically motivated approach directly relates to the underlying circuit structure, hence allowing for a signif- icantly more detailed characterization of application perfor- mance under scaled frequency / voltage (including supply noise). The model uses gate level timing statistics extracted by dynamic timing analysis from the post place & route netlist of a general-purpose processor to perform instruction- aware fault injections. We employ a 28 nm OpenRISC core as a case study, to demonstrate how statistical fault injec- tion provides a more accurate and realistic analysis of power vs. error performance.
Original languageEnglish
Title of host publicationConference Proceedings of Design Automation Conference
Number of pages6
ISBN (Electronic)978-1-4503-4236-0
Publication statusPublished - 05 Jun 2016
EventDesign Automation Conference - Austin, United States
Duration: 06 Jun 201608 Jun 2016 (Lin to event details online)


ConferenceDesign Automation Conference
Abbreviated titleDAC
CountryUnited States
Internet address

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modelling and Simulation

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