Subpixel interpolation architecture for multistandard video motion estimation

Research output: Contribution to journalArticle

12 Citations (Scopus)

Abstract

A new reconfigurable subpixel interpolation architecture for multistandard (e.g., MPEG-2, MPEG-4, H.264, and AVS) video motion estimation (ME) is presented. This exploits the mixed use of parallel and serial-input FIR filters to achieve high throughput rate and efficient silicon utilization. Silicon design studies show that this can be implemented using 34.8 × 10 3 gates with area and performance that compares very favorably with specific fixed solutions, e.g., for the H.264 standard alone. This can support SDTV and HDTV applications when implemented in 0.18 µm CMOS technology, with further performance enhancements achievable at 0.13 µm and below. © 2009 IEEE.
Original languageEnglish
Article number5159433
Pages (from-to)1897-1901
Number of pages5
JournalIEEE Transactions on Circuits and Systems for Video Technology
Volume19
Issue number12
DOIs
Publication statusPublished - Dec 2009

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Media Technology

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