Abstract
Methods are presented for developing synthesisable FFT cores. These are based on a modular approach in which parameterisable blocks are cascaded to implement the computations required across a range of typical FFT signal flow graphs. The underlying architectural approach combines the use of a digital serial data organisation with generic commutator blocks to produce systems that offer 100% processor utilisation with storage requirements less than previous designs. The approach has been used to create generators for the automated synthesis of FFT cores that are portable across a broad range of silicon technologies. Resulting chip designs are competitive with manual methods but with significant reductions in design times.
Original language | English |
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Title of host publication | SIPS 97 - 1997 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS: DESIGN AND IMPLEMENTATION |
Editors | MK Ibrahim, P Pirsch, J McCanny |
Place of Publication | NEW YORK |
Publisher | Ashgate Publishing Ltd |
Pages | 351-363 |
Number of pages | 13 |
ISBN (Print) | 0-7803-3806-5 |
Publication status | Published - 1997 |
Event | 1997 IEEE Workshop on Signal Processing Systems (SiPS 97) - Design and Implementation - LEICESTER, United Kingdom Duration: 03 Nov 1997 → 05 Nov 1997 |
Conference
Conference | 1997 IEEE Workshop on Signal Processing Systems (SiPS 97) - Design and Implementation |
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Country/Territory | United Kingdom |
City | LEICESTER |
Period | 03/11/1997 → 05/11/1997 |