Synthesisable FFT cores

TJ Ding, JV McCanny, Yi Hu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Methods are presented for developing synthesisable FFT cores. These are based on a modular approach in which parameterisable blocks are cascaded to implement the computations required across a range of typical FFT signal flow graphs. The underlying architectural approach combines the use of a digital serial data organisation with generic commutator blocks to produce systems that offer 100% processor utilisation with storage requirements less than previous designs. The approach has been used to create generators for the automated synthesis of FFT cores that are portable across a broad range of silicon technologies. Resulting chip designs are competitive with manual methods but with significant reductions in design times.

Original languageEnglish
Title of host publicationSIPS 97 - 1997 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS: DESIGN AND IMPLEMENTATION
EditorsMK Ibrahim, P Pirsch, J McCanny
Place of PublicationNEW YORK
PublisherAshgate Publishing
Pages351-363
Number of pages13
ISBN (Print)0-7803-3806-5
Publication statusPublished - 1997
Event1997 IEEE Workshop on Signal Processing Systems (SiPS 97) - Design and Implementation - LEICESTER, United Kingdom
Duration: 03 Nov 199705 Nov 1997

Conference

Conference1997 IEEE Workshop on Signal Processing Systems (SiPS 97) - Design and Implementation
CountryUnited Kingdom
CityLEICESTER
Period03/11/199705/11/1997

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