Methods are presented for developing synthesizable FFT cores. These are based on a modular approach in which parameterizable blocks are cascaded to implement the computations required across a range of typical FFT signal flow graphs. The underlying architectural approach combines the use of a digital serial data organization with generic commutator blocks to produce systems that offer 100% processor utilization with storage requirements less than previous designs. The approach has been used to create generators for the automated synthesis of FFT cores that are portable across a broad range of silicon technologies. Resulting chip designs are competitive with manual methods but with significant reductions in design times.
|Title of host publication||Signal Processing Systems - Design and implementation, IEEE Signal Processing Society Press, eds. M. Ibrahim, P. Pirsch and J V McCanny|
|Number of pages||13|
|Publication status||Published - 01 Jan 1997|