Synthesizable FFT cores

Tiong Jiu Ding, John V. McCanny, Yi Hu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Methods are presented for developing synthesizable FFT cores. These are based on a modular approach in which parameterizable blocks are cascaded to implement the computations required across a range of typical FFT signal flow graphs. The underlying architectural approach combines the use of a digital serial data organization with generic commutator blocks to produce systems that offer 100% processor utilization with storage requirements less than previous designs. The approach has been used to create generators for the automated synthesis of FFT cores that are portable across a broad range of silicon technologies. Resulting chip designs are competitive with manual methods but with significant reductions in design times.
Original languageEnglish
Title of host publicationSignal Processing Systems - Design and implementation, IEEE Signal Processing Society Press, eds. M. Ibrahim, P. Pirsch and J V McCanny
Pages351-363
Number of pages13
Publication statusPublished - 01 Jan 1997

Bibliographical note

Copyright 2004 Elsevier Science B.V., Amsterdam. All rights reserved.

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