Synthesizable high performance adaptive equaliser and viterbi decoder for the class-IV PRML channel

BDE Smith*, JV McCanny

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The design and VLSI implementation of two key components of the class-IV partial response maximum likelihood channel (PR-IV) the adaptive filter and the Viterbi decoder are described. These blocks are implemented using parameterised VHDL modules, from a library of common digital signal processing (DSP) and arithmetic functions. Design studies, based on 0.6 micron 3.3V standard cell processes, indicate that worst case sampling rates of 49 mega-samples per second are achievable for this system, with proportionally high sampling rates for full custom designs and smaller dimension processes. Significant increases in the sampling rate, from 49 MHz to approximately 180 MHz, can be achieved by operating four filter modules in parallel, and this implementation has 50% lower power consumption than a pipelined filter operating at the same speed.

Original languageEnglish
Title of host publicationICECS 96 - PROCEEDINGS OF THE THIRD IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS, AND SYSTEMS, VOLS 1 AND 2
Place of PublicationNEW YORK
PublisherAshgate Publishing
Pages25-28
Number of pages4
ISBN (Print)0-7803-3650-X
Publication statusPublished - 1996
Event3rd IEEE International Conference on Electronics, Circuits, and Systems (ICECS 96) - Rhodes, Greece
Duration: 13 Oct 199616 Oct 1996

Conference

Conference3rd IEEE International Conference on Electronics, Circuits, and Systems (ICECS 96)
CountryGreece
CityRhodes
Period13/10/199616/10/1996

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