Synthesizable high performance adaptive equalizer and Viterbi decoder for the class-IV PRML channel

B. D.E. Smith*, J. V. Mc Canny

*Corresponding author for this work

Research output: Contribution to conferencePaper

Abstract

The design and VLSI implementation of two key components of the class-IV partial response maximum likelihood channel (PR-IV), the adaptive filter and the Viterbi decoder are described. These blocks are implemented using parameterized VHDL modules, from a library of common digital signal processing (DSP) and arithmetic functions. Design studies, based on 0.6 micron 3.3 V standard cell processes, indicate that worst case sampling rates of 49 mega-samples per second are achievable for this system, with proportionally high sampling rates for full custom designs and smaller dimension processes. Significant increases in the sampling rate, from 49 MHz to approximately 180 MHz, can be achieved by operating four filter modules in parallel, and this implementation has 50% lower power consumption than a pipelined filter operating at the same speed.

Original languageEnglish
Pages25-28
Number of pages4
Publication statusPublished - 01 Dec 1996
EventProceedings of the 1996 3rd IEEE International Conference on Electronics, Circuits, and Systems, ICECS. Part 2 (of 2) - Rodos, Greece
Duration: 13 Oct 199616 Oct 1996

Conference

ConferenceProceedings of the 1996 3rd IEEE International Conference on Electronics, Circuits, and Systems, ICECS. Part 2 (of 2)
CountryGreece
CityRodos
Period13/10/199616/10/1996

ASJC Scopus subject areas

  • Engineering(all)

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    Smith, B. D. E., & Mc Canny, J. V. (1996). Synthesizable high performance adaptive equalizer and Viterbi decoder for the class-IV PRML channel. 25-28. Paper presented at Proceedings of the 1996 3rd IEEE International Conference on Electronics, Circuits, and Systems, ICECS. Part 2 (of 2), Rodos, Greece.