Systolic array architectures for parameterised multiplexed IIR filters

R.F. Woods, B.P. McGovern, J.V. McCanny

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)


Whilst conventional bit level pipelining introduces an m cycle delay, it does allow m separate computations to be processed at throughput rates comparable to that using word level systolic arrays. We concentrate on exploiting this delay and describe a systematic method for the design of high performance multiplexed IIR filters. Two multiply and accumulate structures are identified based on shift-and-add and carry-save data organisations which can be used as building blocks in the design of IIR filters. By replacing the word level multiply and accumulate units in word level systolic structures with their equivalent bit level circuits and introducing latches to ensure correct timing, numerous architectures can be designed that process multiplexed data directly without any additional circuit overhead.
Original languageEnglish
JournalIEE Colloquium (Digest)
Issue number95
Publication statusPublished - 01 Jan 1990

Bibliographical note

Copyright 2004 Elsevier B.V., All rights reserved.


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