Systolic building block for high performance recursive filtering

R.F. Woods, S.C. Knowles, J.V. McCanny, J.G. McWhirter

Research output: Chapter in Book/Report/Conference proceedingOther chapter contribution

Abstract

A novel bit level systolic array is presented that can be used as a building block in the construction of recursive digital filters. The circuit accepts bit-parallel input data, is pipelined at the bit level, and exhibits a very high throughput rate. The most important feature of the circuit is that it allows recursive operations to be implemented directly without incurring the large m cycle latency (where m is approximately the word length) normally associated with such systems. The use of this circuit in the construction of both first- and second-order IIR (infinite-impulse-response) filters is described.
Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Pages2761-2764
Number of pages4
Volume3
Publication statusPublished - 01 Jan 1988

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  • Cite this

    Woods, R. F., Knowles, S. C., McCanny, J. V., & McWhirter, J. G. (1988). Systolic building block for high performance recursive filtering. In Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 3, pp. 2761-2764)