A novel bit level systolic array is presented that can be used as a building block in the construction of recursive digital filters. The circuit accepts bit-parallel input data, is pipelined at the bit level, and exhibits a very high throughput rate. The most important feature of the circuit is that it allows recursive operations to be implemented directly without incurring the large m cycle latency (where m is approximately the word length) normally associated with such systems. The use of this circuit in the construction of both first- and second-order IIR (infinite-impulse-response) filters is described.
|Title of host publication||Proceedings - IEEE International Symposium on Circuits and Systems|
|Number of pages||4|
|Publication status||Published - 01 Jan 1988|
Woods, R. F., Knowles, S. C., McCanny, J. V., & McWhirter, J. G. (1988). Systolic building block for high performance recursive filtering. In Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 3, pp. 2761-2764)