SYSTOLIC IIR FILTERS WITH BIT LEVEL PIPELINING.

R.F. Woods, S.C. Knowles, J.V. McCanny, J.G. McWhirter

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

A novel bit-level systolic array architecture for implementing first-order IIR filter sections is presented. A latency of only two clock cycles is achieved by using a radix-4 redundant number representation, performing the recursive computation most-significant-digit first, and feeding back each digit of the result as soon as it is available.
Original languageEnglish
Pages (from-to)2072-2075
Number of pages4
JournalICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Publication statusPublished - 01 Jan 1988

Bibliographical note

Copyright 2004 Elsevier B.V., All rights reserved.

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