A novel bit-level systolic array architecture for implementing first-order IIR filter sections is presented. A latency of only two clock cycles is achieved by using a radix-4 redundant number representation, performing the recursive computation most-significant-digit first, and feeding back each digit of the result as soon as it is available.
|Number of pages||4|
|Journal||ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings|
|Publication status||Published - 01 Jan 1988|
Bibliographical noteCopyright 2004 Elsevier B.V., All rights reserved.
Woods, R. F., Knowles, S. C., McCanny, J. V., & McWhirter, J. G. (1988). SYSTOLIC IIR FILTERS WITH BIT LEVEL PIPELINING. ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings, 2072-2075.