Systolic inner product arrays with automatic word rounding

M. Yan*, J. V. Mc Canny

*Corresponding author for this work

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

In this paper, we show how word rounding techniques can be efficiently used to reduce/eliminate the guard band in systolic Inner Product Array (IPA) circuits. This results in a significant improvement in circuit throughput rate. By incorporating a shift-truncation module either in the main array cells or in the accumulator cells, two different versions of an Automatic-Rounding IPA can be produced-the unidirectional ARIPA circuit and the orthogonal ARIPA circuit. It is shown that the proposed method requires considerably less hardware and has a higher degree of regularity when compared with techniques previously proposed. Maximum system word length reduction can be achieved with the modified unidirectional ARIPA circuit at a slight increase in overall circuit complexity. This allows maximum performance to be achieved.

Original languageEnglish
Pages (from-to)227-242
Number of pages16
JournalJournal of VLSI Signal Processing
Volume4
Issue number2-3
DOIs
Publication statusPublished - 01 May 1992

ASJC Scopus subject areas

  • Signal Processing

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