Abstract
The authors present a VLSI circuit for implementing wave digital filter (WDF) two-port adaptors. Considerable speedups over conventional designs have been obtained using fine grained pipelining. This has been achieved through the use of most significant bit (MSB) first carry-save arithmetic, which allows systems to be designed in which latency L is small and independent of either coefficient or input data wordlength. L is determined by the online delay associated with the computation required at each node in the circuit (in this case a multiply/add plus two separate additions). This in turn means that pipelining can be used to considerably enhance the sampling rate of a recursive digital filter. The level of pipelining which will offer enhancement is determined by L and is fine-grained rather than bit level. In the case of the circuit considered, L = 3. For this reason pipeline delays (half latches) have been introduced between every two rows of cells to produce a system with a once every cycle sample rate.
Original language | English |
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Title of host publication | Proceedings of the 1990 International Conference Application Specific Array Processors |
Place of Publication | Piscataway, NJ, United States |
Publisher | IEEE Computer Society |
Pages | 379-388 |
Number of pages | 10 |
ISBN (Print) | 0818690895 |
Publication status | Published - 01 Jan 1991 |
Event | Proceedings of the 1990 International Conference on Application Specific Array Processors - NJ, Princeton , United States Duration: 05 Sep 1990 → 07 Sep 1990 |
Conference
Conference | Proceedings of the 1990 International Conference on Application Specific Array Processors |
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Country | United States |
City | Princeton |
Period | 05/09/1990 → 07/09/1990 |
ASJC Scopus subject areas
- Engineering(all)