Systolic two-port adaptor for high performance wave digital filtering

Rajinder Jit Singh*, J. V. McCanny

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)


The authors present a VLSI circuit for implementing wave digital filter (WDF) two-port adaptors. Considerable speedups over conventional designs have been obtained using fine grained pipelining. This has been achieved through the use of most significant bit (MSB) first carry-save arithmetic, which allows systems to be designed in which latency L is small and independent of either coefficient or input data wordlength. L is determined by the online delay associated with the computation required at each node in the circuit (in this case a multiply/add plus two separate additions). This in turn means that pipelining can be used to considerably enhance the sampling rate of a recursive digital filter. The level of pipelining which will offer enhancement is determined by L and is fine-grained rather than bit level. In the case of the circuit considered, L = 3. For this reason pipeline delays (half latches) have been introduced between every two rows of cells to produce a system with a once every cycle sample rate.

Original languageEnglish
Title of host publicationProceedings of the 1990 International Conference Application Specific Array Processors
Place of PublicationPiscataway, NJ, United States
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages10
ISBN (Print)0818690895
Publication statusPublished - 01 Jan 1991
EventProceedings of the 1990 International Conference on Application Specific Array Processors - NJ, Princeton , United States
Duration: 05 Sept 199007 Sept 1990


ConferenceProceedings of the 1990 International Conference on Application Specific Array Processors
Country/TerritoryUnited States

ASJC Scopus subject areas

  • Engineering(all)


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