Systolic VLSI compiler (SVC) for high performance vector quantisation chips

Y. Hu, J.V. McCanny, M. Yan

Research output: Chapter in Book/Report/Conference proceedingOther chapter contribution

2 Citations (Scopus)

Abstract

An overview is given of a systolic VLSI compiler (SVC) tool currently under development for the automated design of high performance digital signal processing (DSP) chips. Attention is focused on the design of systolic vector quantization chips for use in both speech and image coding systems. The software in question consists of a cell library, silicon assemblers, simulators, test pattern generators, and a specially designed graphics shell interface which makes it expandable and user friendly. It allows very high performance digital coding systems to be rapidly designed in VLSI.
Original languageEnglish
Title of host publicationIEEE Computer Society Press, "Application Specific Array Processors" eds. S Y Kung, E S Swartzlander Jr, J Fortes and K W Przytula
Pages145-155
Number of pages11
Publication statusPublished - 01 Jan 1991

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