One of the problems in future processors will be the resource conflicts caused by several load/store units competing to access the same cache bank. The traditional approach for handling this case is by introducing buffers combined with a cross-bar. This approach suffers from (i) the non-deterministic latency of a load/store and (ii) the extra latency caused by the cross-bar and the buffer management. A deterministic latency is of the utmost importance for the forwarding mechanism of out-of-order processors because it enables back-to-back operation of instructions. We propose a technique by which we eliminate the buffers and cross-bars from the critical path of the load/store execution. This results in both, a low and a deterministic latency. Our solution consists of predicting which bank is to be accessed. Only in the case of a wrong prediction a penalty results.
|Number of pages||12|
|Publication status||Published - 01 Dec 1999|
|Event||The 6th International Symposium on High-Performance Computer Architecture (HPCA-6) - Toulouse, France|
Duration: 08 Jan 2000 → 12 Jan 2000
|Conference||The 6th International Symposium on High-Performance Computer Architecture (HPCA-6)|
|Period||08/01/2000 → 12/01/2000|
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