The design of a VLSI array processor chip for computing the basic arithmetic operations

S. E. McQuillan; J. V. McCanny; R. F. Woods; J. Dowling

doi:10.1109/VLSISP.1992.639173

The design of a VLSI array processor chip for computing the basic arithmetic operations

S. E. McQuillan, J. V. McCanny, R. F. Woods, J. Dowling

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The design of a VLSI array processor chip to perform multiplication, division and square root operations is described. The array architecture on which the chip is based is the hardware description of a unified algorithm that combines the basic arithmetic operations. Through the use of a redundant number system and fine grain pipelining, the execution time of each operation is identical and independent of the wordlength. The chip has been designed using a 1.5 micron, double metal CMOS technology, operates on 16 bit sign magnitude data and has a throughput rate of 40 Megasamples per second for each operation.

Original language	English
Title of host publication	Workshop on VLSI Signal Processing 1992
Editors	Wojtek Przytula, Kung Yao, Rajeev Jain, Jan Rabaey
Place of Publication	NEW YORK
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	61-70
Number of pages	10
ISBN (Electronic)	0780308115, 9780780308114
ISBN (Print)	0-7803-0811-5
DOIs	https://doi.org/10.1109/VLSISP.1992.639173
Publication status	Published - 1992
Externally published	Yes
Event	6th IEEE Workshop on VLSI Signal Processing - Los Angeles, United States Duration: 28 Oct 1992 → 30 Oct 1992

Conference

Conference	6th IEEE Workshop on VLSI Signal Processing
Country/Territory	United States
City	Los Angeles
Period	28/10/1992 → 30/10/1992

ASJC Scopus subject areas

Signal Processing
Electrical and Electronic Engineering
Applied Mathematics

Access to Document

10.1109/VLSISP.1992.639173

Cite this

McQuillan, S. E., McCanny, J. V., Woods, R. F., & Dowling, J. (1992). The design of a VLSI array processor chip for computing the basic arithmetic operations. In W. Przytula, K. Yao, R. Jain, & J. Rabaey (Eds.), Workshop on VLSI Signal Processing 1992 (pp. 61-70). [639173] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSISP.1992.639173

@inproceedings{a25aba3c1d07478eb7014d564767bbb3,

title = "The design of a VLSI array processor chip for computing the basic arithmetic operations",

abstract = "The design of a VLSI array processor chip to perform multiplication, division and square root operations is described. The array architecture on which the chip is based is the hardware description of a unified algorithm that combines the basic arithmetic operations. Through the use of a redundant number system and fine grain pipelining, the execution time of each operation is identical and independent of the wordlength. The chip has been designed using a 1.5 micron, double metal CMOS technology, operates on 16 bit sign magnitude data and has a throughput rate of 40 Megasamples per second for each operation.",

author = "McQuillan, {S. E.} and McCanny, {J. V.} and Woods, {R. F.} and J. Dowling",

year = "1992",

doi = "10.1109/VLSISP.1992.639173",

language = "English",

isbn = "0-7803-0811-5",

pages = "61--70",

editor = "Wojtek Przytula and Kung Yao and Rajeev Jain and Jan Rabaey",

booktitle = "Workshop on VLSI Signal Processing 1992",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "6th IEEE Workshop on VLSI Signal Processing ; Conference date: 28-10-1992 Through 30-10-1992",

}

McQuillan, SE, McCanny, JV , Woods, RF & Dowling, J 1992, The design of a VLSI array processor chip for computing the basic arithmetic operations. in W Przytula, K Yao, R Jain & J Rabaey (eds), Workshop on VLSI Signal Processing 1992., 639173, Institute of Electrical and Electronics Engineers Inc., NEW YORK, pp. 61-70, 6th IEEE Workshop on VLSI Signal Processing, Los Angeles, United States, 28/10/1992. https://doi.org/10.1109/VLSISP.1992.639173

The design of a VLSI array processor chip for computing the basic arithmetic operations. / McQuillan, S. E.; McCanny, J. V.; Woods, R. F. et al.

Workshop on VLSI Signal Processing 1992. ed. / Wojtek Przytula; Kung Yao; Rajeev Jain; Jan Rabaey. NEW YORK : Institute of Electrical and Electronics Engineers Inc., 1992. p. 61-70 639173.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - The design of a VLSI array processor chip for computing the basic arithmetic operations

AU - McQuillan, S. E.

AU - McCanny, J. V.

AU - Woods, R. F.

AU - Dowling, J.

PY - 1992

Y1 - 1992

N2 - The design of a VLSI array processor chip to perform multiplication, division and square root operations is described. The array architecture on which the chip is based is the hardware description of a unified algorithm that combines the basic arithmetic operations. Through the use of a redundant number system and fine grain pipelining, the execution time of each operation is identical and independent of the wordlength. The chip has been designed using a 1.5 micron, double metal CMOS technology, operates on 16 bit sign magnitude data and has a throughput rate of 40 Megasamples per second for each operation.

AB - The design of a VLSI array processor chip to perform multiplication, division and square root operations is described. The array architecture on which the chip is based is the hardware description of a unified algorithm that combines the basic arithmetic operations. Through the use of a redundant number system and fine grain pipelining, the execution time of each operation is identical and independent of the wordlength. The chip has been designed using a 1.5 micron, double metal CMOS technology, operates on 16 bit sign magnitude data and has a throughput rate of 40 Megasamples per second for each operation.

UR - http://www.scopus.com/inward/record.url?scp=85068159773&partnerID=8YFLogxK

U2 - 10.1109/VLSISP.1992.639173

DO - 10.1109/VLSISP.1992.639173

M3 - Conference contribution

SN - 0-7803-0811-5

SP - 61

EP - 70

BT - Workshop on VLSI Signal Processing 1992

A2 - Przytula, Wojtek

A2 - Yao, Kung

A2 - Jain, Rajeev

A2 - Rabaey, Jan

PB - Institute of Electrical and Electronics Engineers Inc.

CY - NEW YORK

T2 - 6th IEEE Workshop on VLSI Signal Processing

Y2 - 28 October 1992 through 30 October 1992

ER -

The design of a VLSI array processor chip for computing the basic arithmetic operations

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ASJC Scopus subject areas

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