The design of a VLSI array processor chip for computing the basic arithmetic operations

S. E. McQuillan, J. V. McCanny, R. F. Woods, J. Dowling

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The design of a VLSI array processor chip to perform multiplication, division and square root operations is described. The array architecture on which the chip is based is the hardware description of a unified algorithm that combines the basic arithmetic operations. Through the use of a redundant number system and fine grain pipelining, the execution time of each operation is identical and independent of the wordlength. The chip has been designed using a 1.5 micron, double metal CMOS technology, operates on 16 bit sign magnitude data and has a throughput rate of 40 Megasamples per second for each operation.

Original languageEnglish
Title of host publicationWorkshop on VLSI Signal Processing 1992
EditorsWojtek Przytula, Kung Yao, Rajeev Jain, Jan Rabaey
Place of PublicationNEW YORK
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages61-70
Number of pages10
ISBN (Electronic)0780308115, 9780780308114
ISBN (Print)0-7803-0811-5
DOIs
Publication statusPublished - 1992
Externally publishedYes
Event6th IEEE Workshop on VLSI Signal Processing - Los Angeles, United States
Duration: 28 Oct 199230 Oct 1992

Conference

Conference6th IEEE Workshop on VLSI Signal Processing
CountryUnited States
CityLos Angeles
Period28/10/199230/10/1992

ASJC Scopus subject areas

  • Signal Processing
  • Electrical and Electronic Engineering
  • Applied Mathematics

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